AMD SC2200 User Manual

32580B

• PnP Configuration Register structure

• Flexible resource allocation for all logical devices:

— Relocatable base address
— 9 parallel IRQ routing options
— 3 optional 8-bit DMA channels (where applicable)

• Software or hardware control

• Enhanced Parallel Port (EPP) compatible with version 

EPP 1.9 and IEEE 1284 compliant

• EPP support for version EPP 1.7 of the Xircom specifi-

cation

• EPP support as mode 4 of the Extended Capabilities 

Port (ECP)

• IEEE 1284 compliant ECP, including level 2

• Selection of internal pull-up or pull-down resistor for 

Paper End (PE) pin

• PCI bus utilization reduction by supporting a demand 

DMA mode mechanism and a DMA fairness mechanism

• Protection circuit that prevents damage to the Parallel 

Port when a printer connected to it powers up or is oper-
ated at high voltages, even if the device is in power-
down

• Output buffers that can sink and source 14 mA

• 16550A compatible (SIN1, SOUT1, DTR1#/BOUT1 

signals only)

• 16550A compatible

• Serial Port 3

— SIN and SOUT signals only
— Data rate of up to 1.5 Mbps
— Software compatible with the 16550A and the 16450
— Shadow register support for write-only bit monitoring
— DMA support

• IR Communication Port

— IrDA 1.1 and 1.0 compatible
— Data rate of up to 115.2 Kbps (HP-SIR)
— Data rate of 1.152 Mbps (MIR)
— Data rate of 4.0 Mbps (FIR)
— Selectable internal or external modulation/demodula-

tion (ASK-IR and DASK-IR options of SHARP-IR)

— Consumer-IR (TV-Remote) mode
— Consumer Remote Control supports RC-5, RC-6, 

NEC, RCA and RECS 80

— DMA support

• Power-up request upon detection of RI2#, CEIR, or 

SDATA_IN2 activity:
— Optional routing of power-up request on IRQ line

• Pre-programmed CEIR address in a pre-selected 

standard (any NEC, RCA or RC-5)

• Powered by V

SB 

• Battery-backed wakeup setup

• Power-fail recovery support

• A modifiable address that is referenced by a 16-bit 

programmable register

• DS1287, MC146818 and PC87911 compatibility

• 242 bytes of battery backed up CMOS RAM in two 

banks

• Selective lock mechanisms for the CMOS RAM

• Battery backed up century calendar in days, day of the 

week, date of month, months, years and century, with 
automatic leap-year adjustment

• Battery backed-up time of day in seconds, minutes and 

hours that allows a 12 or 24 hour format and adjust-
ments for daylight savings time

• BCD or binary format for time keeping

• Three different maskable interrupt flags: 

— Periodic interrupts - At intervals from 122 msec to 

500 msec

— Time-of-Month alarm - At intervals from once per 

second to once per month

— Update Ended Interrupt - Once per second upon 

completion of update

• Separate battery pin, 3.0V operation that includes an 

internal UL protection resistor

• 7 µA typical power consumption during power down

• Double-buffer time registers

• Y2K Compliant

• 48 MHz clock input

• On-chip low frequency clock generator for wakeup

• 32.768 KHz crystal with an internal frequency multiplier 

to generate all required internal frequencies