AMD 10 User Manual
36
Electrical Data
Chapter 8
AMD Athlon™ XP Processor Model 10 Data Sheet
26237C—May 2003
Preliminary Information
8.10
General AC and DC Characteristics
Table 16 shows the AMD Athlon XP processor model 10 AC and
DC characteristics of the Southbridge, JTAG, test, and miscel-
laneous pins.
DC characteristics of the Southbridge, JTAG, test, and miscel-
laneous pins.
Table 16. General AC and DC Characteristics
Symbol
Parameter Description
Condition
Min
Max
Units
Notes
V
IH
Input High Voltage
(V
CC_CORE
/ 2) +
200 mV
V
CC_CORE
+
300 mV
V
1, 2
V
IL
Input Low Voltage
–300
350
mV
1, 2
V
OH
Output High Voltage
V
CC_CORE
–
400
V
CC_CORE
+
300
mV
V
OL
Output Low Voltage
–300
400
mV
I
LEAK_P
Tristate Leakage Pullup
V
IN
= VSS
(Ground)
–1
mA
I
LEAK_N
Tristate Leakage Pulldown
V
IN
= V
CC_CORE
Nominal
600
µA
I
OH
Output High Current
–6
mA
3
I
OL
Output Low Current
6
mA
3
T
SU
Sync Input Setup Time
2.0
ns
4, 5
T
HD
Sync Input Hold Time
0.0
ps
4, 5
T
DELAY
Output Delay with respect to RSTCLK
0.0
6.1
ns
5
Notes:
1. Characterized across DC supply voltage range.
2. Values specified at nominal V
CC_CORE
. Scale parameters between V
CC_CORE.
minimum and V
CC_CORE.
maximum.
3. I
OL
and I
OH
are measured at V
OL
maximum and V
OH
minimum, respectively.
4. Synchronous inputs/outputs are specified with respect to RSTCLK and RSTCK# at the pins.
5. These are aggregate numbers.
6. Edge rates indicate the range over which inputs were characterized.
7. In asynchronous operation, the signal must persist for this time to enable capture.
8. This value assumes RSTCLK period is 10 ns ==> TBIT = 2*fRST.
9. The approximate value for standard case in normal mode operation.
10. This value is dependent on RSTCLK frequency, divisors, Low Power mode, and core frequency.
11. Reassertions of the signal within this time are not guaranteed to be seen by the core.
12. This value assumes that the skew between RSTCLK and K7CLKOUT is much less than one phase.
13. This value assumes RSTCLK and K7CLKOUT are running at the same frequency, though the processor is capable of other
configurations.
14. Time to valid is for any open-drain pins. See requirements 7 and 8 in the “Power-Up Timing Requirements“ chapter for more
information.