Texas Instruments TMS320C2XX User Manual
ZALR
Zero Low Accumulator and Load High Accumulator With Rounding
7-196
Syntax
ZALR
dma
Direct addressing
ZALR
ind [, ARn]
Indirect addressing
Operands
dma:
7 LSBs of the data-memory address
n:
Value from 0 to 7 designating the next auxiliary register
ind:
Select one of the following seven options:
* *+ *– *0+ *0– *BR0+ *BR0–
* *+ *– *0+ *0– *BR0+ *BR0–
ZALR
dma
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
1
0
1
0
0
0
0
dma
ZALR
ind [, ARn]
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
1
0
1
0
0
0
1
ARU
N
NAR
Note:
ARU, N, and NAR are defined in Section 6.3,
Indirect Addressing Mode
(page 6-9).
Execution
Increment PC, then ...
(data-memory address)
(data-memory address)
→
ACC(31:16)
8000h
→
ACC(15:0)
Status Bits
None
Description
To load a data-memory value into the high-order half of the accumulator, the
ZALR instruction rounds the value by adding 1/2 LSB; that is, the 15 low bits
(bits 14–0) of the accumulator are cleared to 0, and bit 15 of the accumulator
is set to 1.
ZALR instruction rounds the value by adding 1/2 LSB; that is, the 15 low bits
(bits 14–0) of the accumulator are cleared to 0, and bit 15 of the accumulator
is set to 1.
Words
1
Cycles for a Single ZALR Instruction
Program
Operand
ROM
DARAM
SARAM
External
DARAM
1
1
1
1+p
SARAM
1
1
1, 2
†
1+p
External
1+d
1+d
1+d
2+d+p
† If the operand and the code are in the same SARAM block
Opcode
Cycles