ARM R4 User Manual

ARM DDI 0363E

8-17

ID013010

In addition, an external error detection scheme might require that data is read and written in 
particular sized chunks. The load/store-64 feature, when enabled for a particular TCM interface, 
causes all loads and stores to the TCM ports to be of 64-bits of data. This feature is also known 
as Read-Modify-Write (RMW), because it causes the processor to generate read-modify-write 
sequences for any store of less than 64-bits. You can enable RMW behavior for each TCM 
interface individually by setting the appropriate bits in the Secondary Auxiliary Control 
Register. See c1, Auxiliary Control Register on page 4-38. You can pin-configure the processor 
to set the enable bits and therefore RMW behavior on reset, by tying off the RMWENRAM 
input as required.

 The  load/store-64  feature is not available on any TCM interface that has been configured with 
32-bit ECC.

The error inputs on each TCM port can also be used to signal other types of error, for example, 
when an address accessed is out of range for the RAM attached to the TCM port. Errors signaled 
on writes from the data-side generate an imprecise abort. All other aborts generated by external 
errors are precise. The type of abort is shown in the appropriate FSR as either precise or 
imprecise parity error.

The processor has a 64-bit AXI slave interface that provides access to the TCM interfaces from 
the AXI bus. This interface is included by default, but can be excluded during configuration of 
the processor.

You can use the slave port for access to the TCM memories. This also enables you to construct 
a system with a consistent view of memory. That is, the TCMs can be available at the same 
address to the processor and to the system bus.

The AXI slave port accesses have lower priority than the LSU or PFU accesses. 

The MPU does not check accesses from the AXI slave. You can configure the processor to 
enable privileged or nonprivileged access to the TCM interfaces from the AXI slave port.

The AXI slave interface does not support locked and exclusive accesses. This means that AXI 
masters, other than the processor, cannot safely use semaphores in the TCMs. Although the 
Cortex-R4 processor can use semaphores in the TCMs for inter-process synchronization, you 
must not use the AXI-slave interface to write to TCM semaphores. The processor has no logic 
to preserve its own exclusivity against such writes.

For more information on the AXI slave interface, see AXI slave interface on page 9-20.