ARM R4 User Manual
Level Two Interface
ARM DDI 0363E
Copyright © 2009 ARM Limited. All rights reserved.
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9.2
AXI master interface
The processor has a single AXI master interface, with one port which is used for:
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I-cache linefills
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D-cache linefills and evictions
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Non-cacheable (NC) Normal-type memory instruction fetches
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NC Normal-type memory data accesses
•
Device and Strongly-ordered type data accesses, normally to peripherals.
The port is 64 bits wide, and conforms to the AXI standard as described in the AMBA AXI
Protocol Specification. Within the AXI standard, the master port uses the AWUSERM and
ARUSERM signals to indicate inner memory attributes.
Protocol Specification. Within the AXI standard, the master port uses the AWUSERM and
ARUSERM signals to indicate inner memory attributes.
The master interface can run at the same frequency as the processor or at a lower synchronous
frequency. See AXI interface clocking on page 3-9 for more information.
frequency. See AXI interface clocking on page 3-9 for more information.
In addition, the AXI master interface produces or checks parity bits for each AXI channel. These
additional signals are not part of the AXI specification. See the Cortex-R4 and Cortex-R4F
Integration Manual for more information.
additional signals are not part of the AXI specification. See the Cortex-R4 and Cortex-R4F
Integration Manual for more information.
Note
References in this section to an AXI slave refer to the AXI slave in the external system which is
connected to the Cortex-R4 AXI master port. This is not necessarily the Cortex-R4 AXI slave
port.
connected to the Cortex-R4 AXI master port. This is not necessarily the Cortex-R4 AXI slave
port.
The following sections describe the attributes of the AXI master interface, and provide
information about the types of burst generated:
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information about the types of burst generated:
•
•
•
•
•
Table 9-1 shows the AXI master interface attributes.
Table 9-1 AXI master interface attributes
Attribute
Value
Comments
Write issuing capability
4
Made up of four outstanding writes that can be evictions, single writes, or write
bursts.
bursts.
a
Read issuing capability
7
Made up of five linefills on the data side, one NC read on the data side, and one
read on the instruction side, that can be NC or linefill.
read on the instruction side, that can be NC or linefill.
Combined issuing capability
11
-
Write ID capability
2
-
Write interleave capability
1
The AXI master interface presents all write data in order.
Read ID capability
7
Made up of five linefills on the data side, one NC read on the data side, and one
linefill or NC read on the instruction side.
linefill or NC read on the instruction side.
a. When there are three outstanding write transactions, only data is issued for the fourth. Only three outstanding write addresses
are issued.