ARM R4 User Manual

ARM DDI 0363E

9-17

ID013010

•

If the data comes from two cache lines, then there are two AXI transactions. For example, 
for 

LDMIA R10, {R0-R5}

 with 

R10 = 0x1010

, the interface might generate one burst of two 

64-bit reads, and one burst of a single 64-bit read, as shown in Table 9-20.

Table 9-21 shows possible values of ARADDRM, ARBURSTM, ARSIZEM, and ARLENM 
for an 

LDR

 or 

LDM

1 to Non-cacheable Normal memory that crosses a cache line boundary.

Table 9-22 shows possible values of ARADDRM, ARBURSTM, ARSIZEM, and ARLENM 
for an 

STRH

 to Non-cacheable Normal memory that crosses a cache line boundary.

A store instruction to Non-cacheable, or write-through Normal memory might not result in an 
AXI transfer because of the merging of store data in the internal buffers.

The STB can detect when it contains more than one write request to the same cache line for 
write-through Cacheable or Non-cacheable Normal memory. This means it can combine the 
data from more than one instruction into a single write burst to improve the efficiency of the 
AXI port. If the AXI master receives several write requests that do not form a single contiguous 
burst it can choose to output a single burst, with the WSTRBW signal low for the bytes that do 
not have any data.

For write accesses to Normal memory, the STB can perform writes out of order, if there are no 
address dependencies. It can do this to best use its ability to merge accesses.

The instruction sequence in Example 9-1 on page 9-18 shows the merging of writes.

0x1010

Incr

64-bit

2 data transfers

0x1020

Incr

64-bit

1 data transfer

0x1D

 (byte 29)

0x1C

Incr

32-bit

1 data transfer

0x00

Incr

32-bit

1 data transfer

0x1E

 (byte 30)

0x1E

Incr

16-bit

1 data transfer

0x00

Incr

64-bit

1 data transfer

0x1F 

(byte 31)

0x1F

Incr

8-bit

1 data transfer

0x00

Incr

32-bit

1 data transfer

0x1F

 (byte 31)

0x1F

Incr

8-bit

1 data transfer

b10000000

0x00

Incr

16-bit

1 data transfer

b00000001