Transcend 512MB DDR DDR266 Non-ECC Memory TS64MSD64V6F5 User Manual

 

 

The TS64MSD64V6F5 is a 64M x 64bits Double Data Rate 

SDRAM high-density for DDR266. The TS64MSD64V6F5 

consists of 16pcs CMOS 32Mx8 bits Double Data Rate 

SDRAMs in 64 pin sTSOP packages and a 2048 bits serial 

EEPROM on a 200-pin printed circuit board. The 

TS64MSD64V6F5 is a Dual In-Line Memory Module and is 

intended for mounting into 200-pin edge connector sockets. 

Synchronous design allows precise cycle control with the 

use of system clock. Data I/O transactions are possible on 

both edges of DQS. Range of operation frequencies, 

programmable latencies allow the same device to be useful 

for a variety of high bandwidth, high performance memory 

system applications. 

 

• 

Power supply : VDD= VDDQ: 2.5V ± 0.2V 

• 

Max clock Freq : 133MHZ. 

• 

Double-data-rate architecture; two data transfers per 

clock cycle 

• 

Differential clock inputs (CK and /CK) 

• 

DLL aligns DQ and DQS transitions with CLK 

transition  

•  Commands entered on each positive CLK edge 
•  Auto and Self Refresh. 
•  Data I/O transactions on both edge of data strobe. 
•  Serial Presence Detect (SPD) with serial EEPROM   
•    SSTL-2 compatible inputs and outputs. 
•    MRS cycle with address key programs. 

          CAS Latency (Access from column address) : 2.5 

     Burst Length (2,4,8) 

     Data Sequence (Sequential & Interleave) 

Placement 
 

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