Transcend 128MB SDRAM 144Pin SO-DIMM PC133 Unbuffer Non-ECC Memory TS16MSS64V6C User Manual
Product codes
TS16MSS64V6C
T
T
T
S
S
S
1
1
1
6
6
6
M
M
M
S
S
S
S
S
S
6
6
6
4
4
4
V
V
V
6
6
6
C
C
C
144PIN PC133 Unbuffered SO-DIMM
128MB With 8Mx16 CL3
Description
The TS16MSS64V6C is a 16M bit x 64 Synchronous
Dynamic RAM high-density memory module. The
TS16MSS64V6C consists of 8 piece of CMOS
2Mx16bitsx4banks Synchronous DRAMs in TSOP-II 400mil
packages and a 2048 bits serial EEPROM on a 144-pin
printed circuit board. The TS16MSS64V6C is a Dual
In-Line Memory Module and is intended for mounting into
144-pin edge connector sockets.
TS16MSS64V6C consists of 8 piece of CMOS
2Mx16bitsx4banks Synchronous DRAMs in TSOP-II 400mil
packages and a 2048 bits serial EEPROM on a 144-pin
printed circuit board. The TS16MSS64V6C is a Dual
In-Line Memory Module and is intended for mounting into
144-pin edge connector sockets.
Synchronous design allows precise cycle control with
the use of system clock. I/O transactions are possible on
every clock cycle. Range of operation frequencies,
programmable latencies allows the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
every clock cycle. Range of operation frequencies,
programmable latencies allows the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
Features
• Performance Range : PC133
• Burst Mode Operation.
• Auto and Self Refresh.
• Serial Presence Detect (SPD) with serial
• Burst Mode Operation.
• Auto and Self Refresh.
• Serial Presence Detect (SPD) with serial
EEPROM
• LVTTL compatible inputs and outputs.
• Single 3.3V ± 0.3V power supply.
• MRS cycle with address key programs.
• Single 3.3V ± 0.3V power supply.
• MRS cycle with address key programs.
Latency (Access from column address)
Burst Length (1,2,4,8 & Full Page)
Data Sequence (Sequential & Interleave)
Burst Length (1,2,4,8 & Full Page)
Data Sequence (Sequential & Interleave)
• All inputs are sampled at the positive going edge
of the system clock.
Pin Identification
Symbol
Function
A0~A11 Address
inputs
BA0,BA1 Select
Bank
DQ0~DQ63 Data
inputs/outputs
CLK0,CLK1 Clock
Input
CKE0,CKE1
Clock Enable Input
/CS0,/CS1
Chip Select Input
/RAS
Row address strobe
/CAS
Column address strobe
/WE Write
Enable
DQM0~7 DQM
Vcc Power
Supply
Vss Ground
SDA
Serial Address / Data I/O
SCL Serial
Clock
NC No
Connection
Transcend information Inc.
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