Motorola CPCI-6020 User Manual
CPCI-6020 CompactPCI Single Board Computer Installation and Use (6806800A51C)
Functional Description
Harrier A, Channel 0 - Onboard Bank A Flash
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4.8.1
Harrier A, Channel 0 - Onboard Bank A Flash
The CPCI-6020 contains one bank of flash memory soldered onboard. Bank A consists of a
single Intel Strata Flash P30 16-bit flash, providing 32 MB of memory. The following table
defines the flash type and size. The device support spage-read mode operations with an 4-word
page size. Flash Bank A is not ECC protected.
single Intel Strata Flash P30 16-bit flash, providing 32 MB of memory. The following table
defines the flash type and size. The device support spage-read mode operations with an 4-word
page size. Flash Bank A is not ECC protected.
4.8.2
Harrier A, Channel 1 - Socketed Bank B Flash
The CPCI-6020 contains two 32-pin PLCC sockets connected to Harrier A Xport channel 1,
which can be populated with 1 MB of flash memory using AMD AM29LV040B or equivalent
devices. This flash memory appears as flash Bank B to the Harrier A chip. Xport channel 1 is
configured to operate in normal address and data mode where the data alternates every byte
instead of every fourth byte (Hawk data mode). Only 8-bit writes are supported for this bank.
which can be populated with 1 MB of flash memory using AMD AM29LV040B or equivalent
devices. This flash memory appears as flash Bank B to the Harrier A chip. Xport channel 1 is
configured to operate in normal address and data mode where the data alternates every byte
instead of every fourth byte (Hawk data mode). Only 8-bit writes are supported for this bank.
The reset vector may be sourced by either Bank A or Bank B depending on the state of Harrier
Xport 0 reset vector control bit RVEN0. When the RVEN0 bit is cleared, address range
FFF00000-FFFFFFFF maps to Bank B. When RVEN0 bit is set, it maps to Bank A. The default
state uses Bank A for the reset vector. Bank B may be selected by connecting the
BANKB_SEL_L pin to GND. Flash Bank B is not ECC protected.
Xport 0 reset vector control bit RVEN0. When the RVEN0 bit is cleared, address range
FFF00000-FFFFFFFF maps to Bank B. When RVEN0 bit is set, it maps to Bank A. The default
state uses Bank A for the reset vector. Bank B may be selected by connecting the
BANKB_SEL_L pin to GND. Flash Bank B is not ECC protected.
4.8.3
Harrier A, Channel 2 - NVRAM, RTC, External Register Set
The Harrier A Xport 2 interface consists of the STMicroelectronics M48T37V. This device
provides 32 KB of nonvolatile static RAM, a real-time clock and a watchdog function. Refer to
the M48T37V Data Sheets for programming information. The M48T37V consists of two parts:
provides 32 KB of nonvolatile static RAM, a real-time clock and a watchdog function. Refer to
the M48T37V Data Sheets for programming information. The M48T37V consists of two parts:
z
A 44-pin 330mil SO device which contains the RTC, the oscillator, the power fail detection,
the watchdog timer logic, 32 KB of SRAM and gold-plated sockets for the SNAPHAT
battery.
the watchdog timer logic, 32 KB of SRAM and gold-plated sockets for the SNAPHAT
battery.
z
A SNAPHAT that houses the battery and/or the crystal
The output of the watchdog timer is logically ORed onboard to provide a hard reset. This signal
is routed to PLD ORing logic so that this feature may be disabled. Xport 2 is configured to
operate in Harrier 8-bit data mode.
is routed to PLD ORing logic so that this feature may be disabled. Xport 2 is configured to
operate in Harrier 8-bit data mode.
4.8.4
Harrier A, Channel 3
The Xport interface is not used.
4.8.5
Harrier B, Channel 0, 1, 2 and 3
None of the Harrier B Xport Channels are used.
Table 4-4 Bank A Flash Options
Bank A Flash Size
Intel Part
Device Size
Device Width
32 MB
1.8 Volt StrataFlash Memory
256 megabit
16 bits