Epson S1C33L03 User Manual
8 ELECTRICAL CHARACTERISTICS
A-98
EPSON
S1C33L03 PRODUCT PART
Frame Pulse
Line Pulse
DRDY (MOD)
Sync Timing
2
1
t
2
t
1
t
5
t
6
t
8
t
9
t
7
t
14
t
11
t
10
t
12
t
13
t
4
t
3
Line Pulse
Shift Pulse
FPDAT[7:4]
Data Timing
Note:
For this timing diagram FPSMASK (D2/0x39FFE1) is set to "1".
4-bit Single Monochrome Panel AC Timing
Symbol
Parameter
Min.
Typ.
Max.
Unit
t
1
Frame Pulse setup to Line Pulse falling edge
note 2
(note 1)
t
2
Frame Pulse hold from Line Pulse falling edge
9
Ts
t
3
Line Pulse period
note 3
t
4
Line Pulse width
9
Ts
t
5
MOD delay from Line Pulse rising edge
1
Ts
t
6
Shift Pulse falling edge to Line Pulse rising edge
note 4
t
7
Shift Pulse falling edge to Line Pulse falling edge
note 5
t
8
Line Pulse falling edge to Shift Pulse falling edge
t
14
+2
Ts
t
9
Shift Pulse period
4
Ts
t
10
Shift Pulse width low
2
Ts
t
11
Shift Pulse width high
2
Ts
t
12
FPDAT[7:4] setup to Shift Pulse falling edge
2
Ts
t
13
FPDAT[7:4] hold from Shift Pulse falling edge
2
Ts
t
14
Line Pulse falling edge to Shift Pulse rising edge
23
Ts
note) 1.Ts
= pixel clock period
2.t
1min
= t
3min
- 9 (Ts)
3.t
3min
= (LDHSIZE[5:0] + 1)
×
16 + (HNDP[4:0] + 4)
×
8 (Ts)
4.t
6min
= HNDP[4:0]
×
8 + 2 (Ts)
5.t
7min
= HNDP[4:0]
×
8 + 11 (Ts)