Epson S1C33L03 User Manual

The Peripheral Block has a built-in low-speed (OSC1) oscillation circuit.

The low-speed (OSC1) oscillation circuit generates a 32.768-kHz (Typ.) subclock.

The OSC1 clock output by this circuit is delivered to the CLG (clock generator) in the Core Block and is used as

the source clock for the clock timer. It can also be used as a sub-clock for the low-speed (low-power) operation of

the CPU and peripheral circuits (switchable in a program).

Figure 6.1 shows the configuration of the clock system.

Clock

switch

CLKCHG

To CPU 
and BCU

OSC3/PLL

clock

To peripheral 
circuits

Low-speed (OSC1)

oscillation circuit

SOSC1

PF1ON

Oscillation

ON/OFF

OSC1
OSC2

I/O port

Prescaler

Clock timer

FOSC1

(P14)

CLG

Figure 6.1  Configuration of Clock System

The CPU operating clock can be switched to the output (OSC1 clock) of the low-speed (OSC1) oscillation circuit

in a program. Furthermore, the oscillation circuit can be stopped in a program.

If the OSC3 clock is unnecessary such as when performing clock processing only, set the OSC1 clock for operation

of the CPU/peripheral circuits and turn off the high-speed (OSC3) oscillation circuit in order to reduce current

consumption.

The low-speed (OSC1) oscillation circuit does not stop in SLEEP mode.

For the control method when using the OSC1 clock for the operating clock of the peripheral circuits, refer to

"Prescaler".

Table 6.1 lists the I/O pins of the low-speed (OSC1) oscillation circuit.

Table 6.1  I/O Pins of Low-Speed (OSC1) Oscillation Circuit

OSC1

I

Low-speed (OSC1) oscillation input pin
Crystal oscillation or external clock input

OSC2

O

Low-speed (OSC1) oscillation output pin
Crystal oscillation (open when external clock is used)

P14/FOSC1/DCLK

I/O

I/O port / Low-speed (OSC1) oscillation clock output / DCLK signal output