Epson S1C33L03 User Manual

Table 2.6 shows the control bits of the A/D converter.

For details on the I/O memory of the prescaler used to set clocks, refer to "Prescaler". For details on the I/O

memory of the programmable timers used for a trigger, refer to "8-Bit Programmable Timers" or "16-Bit

Programmable Timers".

Table 2.6  Control Bits of A/D Converter

D7

D6

D5

D4

D3

D2

D1

D0

A/D converted data

(low-order 8 bits)

ADD0 = LSB

0x0 to 0x3FF

(low-order 8 bits)

0

0

0

0

0

0

0

0

R

0x0 to 0x3FF

(high-order 2 bits)

–

D7–2

D1

D0

–

A/D converted data

(high-order 2 bits) ADD9 = MSB

–

0

0

–

R

0 when being read.

D7–6

D5

D4

D3

D2

D1

D0

–

A/D conversion mode selection

A/D conversion trigger selection

A/D conversion channel status

1

1

0

0

1

0

1

0

TS[1:0]

–

Trigger

#ADTRG pin

8-bit timer 0

16-bit timer 0

Software

1

1

1

1

0

0

0

0

1

1

0

0

1

1

0

0

1

0

1

0

1

0

1

0

CH[2:0]

Channel

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

–

0

0

0

0

0

0

–

R/W

R/W

R

0 when being read.

1 Continuous 0 Normal

–

1

1

1

1

0

0

0

0

1

1

0

0

1

1

0

0

1

0

1

0

1

0

1

0

CE[2:0]

End channel

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

1

1

1

1

0

0

0

0

1

1

0

0

1

1

0

0

1

0

1

0

1

0

1

0

CS[2:0]

Start channel

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

D7–6

D5

D4

D3

D2

D1

D0

–

A/D converter

end channel selection

A/D converter

start channel selection

–

0

0

0

0

0

0

–

R/W

R/W

0 when being read.

D7–4

D3

D2

D1

D0

–

Conversion-complete flag

A/D enable

A/D conversion control/status

Overwrite error flag

–

–

0

0

0

0

–

R

R/W

R/W

R/W

0 when being read.

Reset when ADD is read.

Reset by writing 0.

1 Enabled

0 Disabled

1 Completed

0 Run/Standby

1 Start/Run

0 Stop

1 Error

0 Normal

D7–2

D1

D0

–

Input signal sampling time setup

–

1

1

0

0

1

0

1

0

ST[1:0]

Sampring time

9 clocks

7 clocks

5 clocks

3 clocks

–

1

1

–

R/W

0 when being read.

Use with 9 clocks.