Epson S1C33L03 User Manual

The trap vector address for an interrupt upon completion of IDMA transfer by default is set to 0x0C00068.

The trap table base address can be changed using the TTBR registers (0x48134 to 0x48137).

Table 3.3 shows the control bits of IDMA.

Table 3.3  Control Bits of IDMA

–

0 to 7

D7–3

D2

D1

D0

reserved

IDMA interrupt level

–

X

X

X

–

R/W

0 when being read.

D7–5

D4

D3

D2

D1

D0

reserved

IDMA

High-speed DMA Ch.3

High-speed DMA Ch.2

High-speed DMA Ch.1

High-speed DMA Ch.0

–

–

0

0

0

0

0

–

R/W

R/W

R/W

R/W

R/W

0 when being read.

1 Enabled

0 Disabled

D7–5

D4

D3

D2

D1

D0

reserved

IDMA

High-speed DMA Ch.3

High-speed DMA Ch.2

High-speed DMA Ch.1

High-speed DMA Ch.0

–

–

X

X

X

X

X

–

R/W

R/W

R/W

R/W

R/W

0 when being read.

1 Factor is 

generated

0 No factor is 

generated

DF

DE

DD

DC

DB

DA

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

IDMA base address

low-order 16 bits

(Initial value: 0x0C003A0)

0

0

0

0

0

0

1

1

1

0

1

0

0

0

0

0

R/W

–

DF–C

DB

DA

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

reserved

IDMA base address

high-order 12 bits

(Initial value: 0x0C003A0)

–

0

0

0

0

1

1

0

0

0

0

0

0

–

R/W

Undefined in read.

0 to 127

D7

D6–0

IDMA start

IDMA channel number

1 IDMA start

0 Stop

0

0

R/W

R/W

–

D7–1

D0

reserved

IDMA enable

1 Enabled

0 Disabled

–

0

–

R/W