Epson S1C33L03 User Manual

The LCD controller uses the BCU clock as the source clock for its pixel clock PCLK and display memory clock

MCLK. The maximum clock frequency that can be supplied to the LCD controller is 25 MHz. The BCU clock

divide ratios can be set using the LCLKSEL[2:0] (D[2:0])/FIFO control register (0x39FFF4), as shown in Table

2.3 below.

LCLKSEL[2:0]

#X2SPD pin

To CPU

CPU_CLK

BCU_CLK

Bus clock

LCDC clock (PCLK, MCLK)

BCU

CLG

1/1 or 1/2

1/1
1/2
1/3
1/4

Figure 2.3  LCDC Clocks

Table 2.3  Selection of LCDC Clocks

0

0

0

Turned off

0

0

1

Turned off

0

1

0

Turned off

0

1

1

Reserved (not allowed)

1

0

0

BCU_CLK

1

0

1

BCU_CLK/2

1

1

0

BCU_CLK/3

1

1

1

BCU_CLK/4