Epson S1C33L03 User Manual
VII LCD CONTROLLER BLOCK: LCD CONTROLLER
S1C33L03 FUNCTION PART
EPSON
B-VII-2-31
A-1
B-VII
LCDC
I/O Memory of LCD Controller
Table 2.21 shows the control bits of the LCD controller. These registers are mapped into area 6 (0x39FFE0 to
0x39FFFD).
Table 2.21 Control Bits of LCD Controller
Name
Address
Register name
Bit
Function
Setting
Init.
R/W
Remarks
PCODE5
PCODE4
PCODE3
PCODE2
PCODE1
PCODE0
RCODE1
RCODE0
D7
D6
D5
D4
D3
D2
D1
D0
Product code
Revision code
0
0
0
0
1
0
0
0
R
R
039FFE0
(B)
Revision code
register
0b000010
–
–
–
LDCOLOR
–
FPSMASK
LDDW1
LDDW0
D7–6
D5
D4–3
D2
D1
D0
reserved
Color/monochrome select
reserved
Mask FPSHIFT signal
LCD data width/format
–
0
–
0
0
0
–
R/W
–
R/W
R/W
0 when being read.
0 when being read.
039FFE1
(B)
1 Color
0 Mono
1 Masked
0 Output
LCDC mode
register 0
1
0
0
x
1
0
LDDW[1:0]
Monochrome
reserved
8 bits
4 bits
1
1
0
0
1
0
1
0
LDDW[1:0]
Color
8 bits/format 2
reserved
8 bits/format 1
4 bits
–
–
BPP1
BPP0
–
DBLANK
FRMRPT
–
INVDISP
D7
D6
D5–4
D3
D2
D1
D0
Bit-per-pixel select
(Display mode)
reserved
Blank display
Frame repeat for EL panel
reserved
Invert display
0
0
–
0
0
–
0
R/W
–
R/W
R/W
–
R/W
0 when being read.
0 when being read.
039FFE2
(B)
1 Repeated
0 Not repeated
1 Inverted
0 Normal
1 Blank
0 Normal
LCDC mode
register 1
1
1
0
0
1
0
1
0
BPP[1:0]
Mode
8 bpp
4 bpp
2 bpp
1 bpp
–
–
–
LCDCEN
LPWREN
–
LPSAVE1
LPSAVE0
D7–6
D5
D4
D3–2
D1
D0
reserved
LCD controller enable
LCDPWR enable
reserved
Power save mode
–
0
0
–
0
0
–
R/W
R/W
–
R/W
0 when being read.
0 when being read.
039FFE3
(B)
1 Enabled
0 Disabled
1 Enabled
0 Disabled
LCDC mode
register 2
1
1
0
0
1
0
1
0
LPSAVE[1:0]
Mode
Normal operation
Doze
reserved
Power save
–
LDHSIZE5
LDHSIZE4
LDHSIZE3
LDHSIZE2
LDHSIZE1
LDHSIZE0
D7–6
D5
D4
D3
D2
D1
D0
reserved
Horizontal panel size
–
0
0
0
0
0
0
–
R/W
0 when being read.
039FFE4
(B)
Horizontal
panel size
register
–
H resolution (pixels)
- 1
16
LDVSIZE7
LDVSIZE6
LDVSIZE5
LDVSIZE4
LDVSIZE3
LDVSIZE2
LDVSIZE1
LDVSIZE0
D7
D6
D5
D4
D3
D2
D1
D0
Vertical panel size
(low-order 8 bits)
0
0
0
0
0
0
0
0
R/W
039FFE5
(B)
Vertical
panel size
register 0
V resolution (lines) - 1
–
LDVSIZE9
LDVSIZE8
D7–2
D1
D0
reserved
Vertical panel size
(high-order 2 bits)
–
0
0
–
R/W
0 when being read.
039FFE6
(B)
Vertical
panel size
register 1
–
V resolution (lines) - 1
–
HNDP4
HNDP3
HNDP2
HNDP1
HNDP0
D7–5
D4
D3
D2
D1
D0
reserved
Horizontal non-display period
–
0
0
0
0
0
–
R/W
0 when being read.
039FFE7
(B)
Horizontal
non-display
period register
–
Non-display period (pixels)
- 4
8