Epson S1C33L03 User Manual

Epson

8 ELECTRICAL CHARACTERISTICS

S1C33L03 PRODUCT PART

EPSON

A-73

A-1

A-8

8.3

DC Characteristics

1) 3.3 V/5.0 V dual power source

(Unless otherwise specified: V

DDE

=5V±0.5V, V

DD

=2.7V to 3.6V, V

SS

=0V, Ta=-40°C to +85°C)

Item

Symbol

Condition

Min.

Typ.

Max.

Unit

∗

Input leakage current

I

LI

-1

–

1

µA

Off-state leakage current

I

OZ

-1

–

1

µA

High-level output voltage

V

OH

I

OH

=-3mA (Type1), I

OH

=-12mA (Type3),

V

DDE

=Min.

V

DDE

-0.4

–

–

V

Low-level output voltage

V

OL

I

OL

=3mA (Type1), I

OL

=12mA (Type3),

V

DDE

=Min.

–

–

0.4

V

High-level input voltage

V

IH

CMOS level, V

DDE

=Max.

3.5

–

–

V

Low-level input voltage

V

IL

CMOS level, V

DDE

=Min.

–

–

1.0

V

Positive trigger input voltage

V

T+

CMOS Schmitt

2.0

–

4.0

V

Negative trigger input voltage

V

T-

CMOS Schmitt

0.8

–

3.1

V

Hysteresis voltage

V

H

CMOS Schmitt

0.3

–

–

V

High-level input voltage

V

IH2

TTL level, V

DDE

=Max.

2.0

–

–

V

Low-level input voltage

V

IL2

TTL level, V

DDE

=Min.

–

–

0.8

V

Pull-up resistor

R

PU

V

I

=0V

60

120

288

k

Ω

Pull-down resistor

R

PD

V

I

=V

DDE

(ICEMD)

30

60

144

k

Ω

Input pin capacitance

C

I

f=1MHz, V

DDE

=0V

–

–

10

pF

Output pin capacitance

C

O

f=1MHz, V

DDE

=0V

–

–

10

pF

I/O pin capacitance

C

IO

f=1MHz, V

DDE

=0V

–

–

10

pF

2) 3.3 V single power source

(Unless otherwise specified: V

DDE

=V

DD

=2.7V to 3.6V, Ta=-40°C to +85°C)

Item

Symbol

Condition

Min.

Typ.

Max.

Unit

∗

Static current consumption

I

DDS

Static state, T

j

=85°C

–

–

90

µA

Input leakage current

I

LI

-1

–

1

µA

Off-state leakage current

I

OZ

-1

–

1

µA

High-level output voltage

V

OH

I

OH

=-2mA (Type1), I

OH

=-6mA (Type2),

I

OH

=-12mA (Type3), V

DD

=Min.

V

DD

-0.4

–

–

V

Low-level output voltage

V

OL

I

OL

=2mA (Type1), I

OL

=6mA (Type2),

I

OL

=12mA (Type3), V

DD

=Min.

–

–

0.4

V

High-level input voltage

V

IH

CMOS level, V

DD

=Max.

2.0

–

–

V

Low-level input voltage

V

IL

CMOS level, V

DD

=Min.

–

–

0.8

V

Positive trigger input voltage

V

T+

LVTTL Schmitt

1.1

–

2.4

V

Negative trigger input voltage

V

T-

LVTTL Schmitt

0.6

–

1.8

V

Hysteresis voltage

V

H

LVTTL Schmitt

0.1

–

–

V

Pull-up resistor

R

PU

V

I

=0V

Other than DSIO

80

200

480

k

Ω

DSIO

40

100

240

k

Ω

Pull-down resistor

R

PD

V

I

=V

DD

(ICEMD)

40

100

240

k

Ω

Input pin capacitance

C

I

f=1MHz, V

DD

=0V

–

–

10

pF

Output pin capacitance

C

O

f=1MHz, V

DD

=0V

–

–

10

pF

I/O pin capacitance

C

IO

f=1MHz, V

DD

=0V

–

–

10

pF

Note: See Appendix B for pin characteristics.