Renesas M16C User Manual

Rev.1.10    Jul 01, 2005    page 71 of 318
REJ09B0124-0110

M16C/6N Group (M16C/6NK, M16C/6NM)

9. Interrupt

This document is under development and its contents are subject to change.

The FLG register and PC in the state in which they were immediately before entering the interrupt

sequence are restored from the stack by executing the REIT instruction at the end of the interrupt routine.

Thereafter the CPU returns to the program which was being executed before accepting the interrupt

request.

Return the other registers saved by a program within the interrupt routine using the POPM or similar

instruction before executing the REIT instruction.

If two or more interrupt requests are generated while executing one instruction, the interrupt request that

has the highest priority is accepted.

For maskable interrupts (peripheral functions), any desired priority level can be selected using the ILVL2

to ILVL0 bits. However, if two or more maskable interrupts have the same priority level, their interrupt

priority is resolved by hardware, with the highest priority interrupt accepted.

The watchdog timer and other special interrupts have their priority levels set in hardware. Figure 9.9

shows the priorities of hardware interrupts.

Software interrupts are not affected by the interrupt priority. If an instruction is executed, control branches

invariably to the interrupt routine.

The interrupt priority resolution circuit is used to select the interrupt with the highest priority among those

requested.

Figure 9.10 shows the circuit that judges the interrupt priority level.

Reset

Oscillation Stop and Re-oscillation Detection

Watchdog Timer

Peripheral Function

Single Step

Address Match

High

Low

NMI

DBC