Texas Instruments 1 User Manual
B-4 MPB Schematic Diagrams
Figure B-1 MPB CPU Board Logic Diagrams (Sheet 3 of 3)
C22
SCD1U
SCD1U
C13
SCD1U
SCD1U
C29
SCD1U
SCD1U
C40
SCD1U
SCD1U
C25
SCD1U
SCD1U
CPU_VEND
CPU_ID2
CPU_ID3
1
1
1
1
2
R14
0R3
0R3
1
2
R2
0R3
0R3
1
2
R3
0R3
0R3
1
2
R12
0R3
0R3
1
2
R11
0R3
0R3
CPU_ID0
CPU_ID1
1
1
Not Installed
C36
SCD1U
SCD1U
C30
SCD1U
SCD1U
R12
R11
R12
SHIGA
SHIGA
R2
R3
RATIO
1
2
R25
36KR3D
R11
SHIVA
CPU
CLOCK
CPU_VOLT0
1
FOR SHIGA
SHIVA NOT INS.
CPU_VOLT1
CPU_THM
CPU_THMG
1
1
1
THERMAL SENSOR
1
2
TH1
TH301
50MHz
60MHz
66MHz
X
O : Install
O
X
X
X : Not install
X
X
O
O
X
X
X1.5
X2.0
X2.5
O
O
X
O
O
X
X
O
C19
SCD1U
C43
SCD1U
C4
SCD1U
C2
SCD1U
VCC_CPU
C9
SCD1U
C21
SCD1U
C16
SCD1U
C12
SCD1U
C6
SCD1U
VCC_CPU
C17
SCD1U
C28
SCD1U
C41
SCD1U
C5
SCD1U
C23
SCD1U
C8
SCD1U
C24
SCD1U
C10
SCD1U
C11
SCD1U
C35
SCD1U
C39
SCD1U
C31
SCD1U
C42
SCD1U
C52
SCD1U
VCC_I/O
1
2
R26
10KR3
10KR3
CPU_THM
C47
SCD1U
SCD1U
CPU_VEND
CPU_ID2
CPU_ID3
FOR SHIVA
SHIGA NOT INS.
1
2
2
3
4
4
5
6
6
7
8
8
9
10
11
10
11
12
13
13
14
15
15
16
17
18
17
18
19
20
J2
HRS-CON18
1
2
R8
33R3
1
2
R9
33R3
1
2
R27
33R3
1
2
R22
33R3
$CPUINIT
$RS#
$PRDY
$TDI
$TDO
$TMS
$TMS
$TCK
$TRST#
$CPURST
VCC_I/O
1
1
2
2
2
2
2
2
SHIVA & SHIGA NOT INS.
DQ
1
CLK/CONV#
2
RST#
3
GND
4
VDD
8
THIGH
7
TLOW
6
TCOM
5
U2
DS1620
CPU_VOLT0
CPU_VOLT1
CPU_THMG
CPU_VOLT1
CPU_THMG