Intel PXA26X User Manual
Intel® PXA26x Processor Family Developer’s Manual
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Liquid Crystal Display Controller
7.6.7.4
LCD Quick Disable Status (QD)
QD is set when LCD enable (LCCR0[ENB]) is cleared and the DMA controller finishes any
current data burst. When QD is set, an interrupt request is made to the interrupt controller (if the
interrupt controller is unmasked (LCCR0[QDM]=0)). This forces the LCD controller to stop
immediately and quit driving the LCD pins. Quick disable is intended for use with sleep shutdown.
current data burst. When QD is set, an interrupt request is made to the interrupt controller (if the
interrupt controller is unmasked (LCCR0[QDM]=0)). This forces the LCD controller to stop
immediately and quit driving the LCD pins. Quick disable is intended for use with sleep shutdown.
7.6.7.5
Output FIFO Underrun Status (OU)
OU is set when an output FIFO is completely empty and the LCD’s data pin driver logic attempts
to fetch data from the FIFO. It is cleared by writing one to the bit. OU is used for single- and dual-
panel displays. In dual-panel mode (LCCR0[SDS]=1), both FIFOs are filled and emptied at the
same time, so that underrun occurs at the same time for both panels. When OU is set, an interrupt
request is made to the interrupt controller (if the interrupt controller is unmasked
(LCCR0[OUM]=0)). Output FIFO underruns are more important that input FIFO underruns,
because they affect the panel.
to fetch data from the FIFO. It is cleared by writing one to the bit. OU is used for single- and dual-
panel displays. In dual-panel mode (LCCR0[SDS]=1), both FIFOs are filled and emptied at the
same time, so that underrun occurs at the same time for both panels. When OU is set, an interrupt
request is made to the interrupt controller (if the interrupt controller is unmasked
(LCCR0[OUM]=0)). Output FIFO underruns are more important that input FIFO underruns,
because they affect the panel.
7.6.7.6
Input FIFO Underrun Upper Panel Status (IUU)
IUU is set when the upper panel’s input FIFO is completely empty and the LCD controller’s pixel
unpacking logic attempts to fetch data from the FIFO. It is cleared by writing one to the bit. IUU is
used in both single-panel (LCCR0[SDS]=0) and dual-panel (SDS=1) modes. When IUU is set, an
interrupt request is made to the interrupt controller (if the interrupt controller is unmasked
(LCCR0[IUM]=0)).
unpacking logic attempts to fetch data from the FIFO. It is cleared by writing one to the bit. IUU is
used in both single-panel (LCCR0[SDS]=0) and dual-panel (SDS=1) modes. When IUU is set, an
interrupt request is made to the interrupt controller (if the interrupt controller is unmasked
(LCCR0[IUM]=0)).
7.6.7.7
Input FIFO Underrun Lower Panel Status (IUL)
IUL, used only in dual-panel mode (LCCR0[SDS]=1), is set when the lower panel’s input FIFO is
completely empty and the LCD controller’s pixel unpacking logic attempts to fetch data from the
FIFO. It is cleared by writing one to the bit. When IUL is set, an interrupt request is made to the
interrupt controller (if the interrupt controller is unmasked (LCCR0[IUM]=0)).
completely empty and the LCD controller’s pixel unpacking logic attempts to fetch data from the
FIFO. It is cleared by writing one to the bit. When IUL is set, an interrupt request is made to the
interrupt controller (if the interrupt controller is unmasked (LCCR0[IUM]=0)).
7.6.7.8
AC Bias Count Status (ABC)
ABC is set each time the AC bias pin (L_BIAS) toggles the number of times specified in the AC
bias pin transitions per interrupt (API) field in LCCR3. If API is programmed with a non-zero
value, a counter is loaded with the value in API and is decremented each time L_BIAS toggles.
When the counter reaches zero, ABC is set, which signals an interrupt request to the interrupt
controller. The counter reloads using the value in API but does not start to decrement again until
ABC is cleared by software.
bias pin transitions per interrupt (API) field in LCCR3. If API is programmed with a non-zero
value, a counter is loaded with the value in API and is decremented each time L_BIAS toggles.
When the counter reaches zero, ABC is set, which signals an interrupt request to the interrupt
controller. The counter reloads using the value in API but does not start to decrement again until
ABC is cleared by software.
7.6.7.9
Bus Error Status (BER)
BER is set when a DMA transfer causes a system bus error. The error is signalled when the DMA
controller attempts to access a reserved or nonexistent memory space. When this occurs, the DMA
controller stops and remains halted until software installs a valid memory address into the
FDADRx register. In dual-channel mode, both channels are stopped. FDADR0 and FDADR1 must
be rewritten to continue LCD operation. BER remains set until cleared by software.
controller attempts to access a reserved or nonexistent memory space. When this occurs, the DMA
controller stops and remains halted until software installs a valid memory address into the
FDADRx register. In dual-channel mode, both channels are stopped. FDADR0 and FDADR1 must
be rewritten to continue LCD operation. BER remains set until cleared by software.