Motorola MC68340 User Manual
3- 4
MC68340 USER’S MANUAL
MOTOROLA
3.1.3 Address Bus (A31–A0)
These signals are outputs that define the address of the byte (or the most significant byte)
to be transferred during a bus cycle. The MC68340 places the address on the bus at the
beginning of a bus cycle. The address is valid while
to be transferred during a bus cycle. The MC68340 places the address on the bus at the
beginning of a bus cycle. The address is valid while
AS
is asserted.
3.1.4 Address Strobe (
AS
)
This output timing signal indicates the validity of many control signals and the address on
the address bus.
the address bus.
AS
is asserted approximately one-half clock cycle after the beginning of
a bus cycle.
3.1.5 Data Bus (D15–D0)
This bidirectional, nonmultiplexed, parallel bus contains the data being transferred to or
from the MC68340. A read or write operation may transfer 8 or 16 bits of data (one or two
bytes) in one bus cycle. During a read cycle, the data is latched by the MC68340 on the
last falling edge of the clock for that bus cycle. For a write cycle, all 16 bits of the data bus
are driven, regardless of the port width or operand size. The MC68340 places the data on
the data bus approximately one-half clock cycle after
from the MC68340. A read or write operation may transfer 8 or 16 bits of data (one or two
bytes) in one bus cycle. During a read cycle, the data is latched by the MC68340 on the
last falling edge of the clock for that bus cycle. For a write cycle, all 16 bits of the data bus
are driven, regardless of the port width or operand size. The MC68340 places the data on
the data bus approximately one-half clock cycle after
AS
is asserted in a write cycle.
3.1.6 Data Strobe (
DS
)
DS
is an output timing signal that applies to the data bus. For a read cycle, the MC68340
asserts
DS
and
AS
simultaneously to signal the external device to place data on the bus.
For a write cycle,
DS
signals to the external device that the data to be written is valid. The
MC68340 asserts
DS
approximately one clock cycle after the assertion of
AS
during a
write cycle.
3.1.7 Bus Cycle Termination Signals
The following signals can terminate a bus cycle.
3.1.7.1 DATA TRANSFER AND SIZE ACKNOWLEDGE SIGNALS (
DSACK1
AND
DSACK0
). During bus cycles, external devices assert
DSACK1
and/or
DSACK0
as part
of the bus protocol. During a read cycle, this signals the MC68340 to terminate the bus
cycle and to latch the data. During a write cycle, this indicates that the external device has
successfully stored the data and that the cycle may terminate. These signals also indicate
to the MC68340 the size of the port for the bus cycle just completed (see Table 3-3). Refer
to 3.3.1 Read Cycle for timing relationships of
cycle and to latch the data. During a write cycle, this indicates that the external device has
successfully stored the data and that the cycle may terminate. These signals also indicate
to the MC68340 the size of the port for the bus cycle just completed (see Table 3-3). Refer
to 3.3.1 Read Cycle for timing relationships of
DSACK1
and
DSACK0
.
Additionally, the system integration module (SIM40) chip select address mask register can
be programmed to internally generate
be programmed to internally generate
DSACK1
and
DSACK0
for external accesses,
eliminating logic required to generate these signals. However, if external
DSACK
≈
signals
are returned earlier than indicated by the DD bits in the chip select address mask register,
the cycle will terminate sooner than programmed. Refer to Section 4 System Integration
Module for additional information. The SIM40 can alternatively be programmed to
generate a fast termination cycle, providing a two-cycle external access. Refer to 3.2.6
Fast Termination Cycles for additional information on these cycles.
the cycle will terminate sooner than programmed. Refer to Section 4 System Integration
Module for additional information. The SIM40 can alternatively be programmed to
generate a fast termination cycle, providing a two-cycle external access. Refer to 3.2.6
Fast Termination Cycles for additional information on these cycles.
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