Motorola MC68340 User Manual
11/2/95
SECTION 1: OVERVIEW
UM Rev 1
MOTOROLA
MC68340 USER'S MANUAL
v
TABLE OF CONTENTS (Continued)
Paragraph
P a g e
Number
Title
Number
2.15
Test Signals.......................................................................................................
2-13
2.15.1
Test Clock (TCK)...........................................................................................
2-13
2.15.2
Test Mode Select (TMS)..............................................................................
2-13
2.15.3
Test Data In (TDI)..........................................................................................
2-13
2.15.4
Test Data Out (TDO).....................................................................................
2-13
2.16
Synthesizer Power (V
CCSYN
)..........................................................................
2-13
2.17
System Power and Ground (V
CC
and GND)................................................
2-13
2.18
Signal Summary...............................................................................................
2-13
Section 3
Bus Operation
3.1
Bus Transfer Signals........................................................................................
3-1
3.1.1
Bus Control Signals .....................................................................................
3-2
3.1.2
Function Code Signals................................................................................
3-3
3.1.3
Address Bus (A31–A0) ................................................................................
3-4
3.1.4
Address Strobe (
AS
)....................................................................................
3-4
3.1.5
Data Bus (D15–D0) ......................................................................................
3-4
3.1.6
Data Strobe (
DS
)...........................................................................................
3-4
3.1.7
Bus Cycle Termination Signals..................................................................
3-4
3.1.7.1
Data Transfer and Size Acknowledge Signals
(
DSACK1
and
DSACK0
).....................................................................
3-4
3.1.7.2
Bus Error (
BERR
).......................................................................................
3-5
3.1.7.3
Autovector (
AVEC
)....................................................................................
3-5
3.2
Data Transfer Mechanism...............................................................................
3-5
3.2.1
Dynamic Bus Sizing.....................................................................................
3-5
3.2.2
Misaligned Operands...................................................................................
3-7
3.2.3
Operand Transfer Cases.............................................................................
3-7
3.2.3.1
Byte Operand to 8-Bit Port, Odd or Even (A0 = X) ..............................
3-7
3.2.3.2
Byte Operand to 16-Bit Port, Even (A0 = 0)..........................................
3-8
3.2.3.3
Byte Operand to 16-Bit Port, Odd (A0 = 1) ...........................................
3-9
3.2.3.4
Word Operand to 8-Bit Port, Aligned .....................................................
3-9
3.2.3.5
Word Operand to 16-Bit Port, Aligned...................................................
3-10
3.2.3.6
Long-word Operand to 8-Bit Port, Aligned...........................................
3-10
3.2.3.7
Long-Word Operand to 16-Bit Port, Aligned ........................................
3-12
3.2.4
Bus Operation................................................................................................
3-14
3.2.5
Synchronous Operation with
DSACK
≈
.....................................................
3-14
3.2.6
Fast Termination Cycles..............................................................................
3-15
3.3
Data Transfer Cycles........................................................................................
3-16
3.3.1
Read Cycle.....................................................................................................
3-16
3.3.2
Write Cycle.....................................................................................................
3-18
3.3.3
Read-Modify-Write Cycle.............................................................................
3-19
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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