Motorola MC68340 User Manual
3- 34
MC68340 USER’S MANUAL
MOTOROLA
3.5.1 Bus Errors
BERR
can be used to abort the bus cycle and the instruction being executed.
BERR
takes
precedence over
DSACK
≈
provided it meets the timing constraints described in Section
11 Electrical Characteristics. If
BERR
does not meet these constraints, it may cause
unpredictable operation of the MC68340. If
BERR
remains asserted into the next bus
cycle, it may cause incorrect operation of that cycle. When
BERR
is issued to terminate a
bus cycle, the MC68340 can enter exception processing immediately following the bus
cycle, or it can defer processing the exception.
cycle, or it can defer processing the exception.
The instruction prefetch mechanism requests instruction words from the bus controller
before it is ready to execute them. If a bus error occurs on an instruction fetch, the
MC68340 does not take the exception until it attempts to use that instruction word. Should
an intervening instruction cause a branch or should a task switch occur, the bus error
exception does not occur. The bus error condition is recognized during a bus cycle in any
of the following cases:
before it is ready to execute them. If a bus error occurs on an instruction fetch, the
MC68340 does not take the exception until it attempts to use that instruction word. Should
an intervening instruction cause a branch or should a task switch occur, the bus error
exception does not occur. The bus error condition is recognized during a bus cycle in any
of the following cases:
•
DSACK
≈
and
HALT
are negated, and
BERR
is asserted.
•
HALT
and
BERR
are negated, and
DSACK
≈
is asserted.
BERR
is then asserted
within one clock cycle (
HALT
remains negated).
•
BERR
and
HALT
are asserted simultaneously, indicating a retry.
When the MC68340 recognizes a bus error condition, it terminates the current bus cycle in
the normal way. Figure 3-17 shows the timing of a bus error for the case in which
the normal way. Figure 3-17 shows the timing of a bus error for the case in which
DSACK
≈
is not asserted. Figure 3-18 shows the timing for a bus error that is asserted
after
DSACK
≈
. Exceptions are taken in both cases. Refer to Section 5 CPU32 for details
of bus error exception processing.
In the second case, in which
BERR
is asserted after
DSACK
≈
is asserted,
BERR
must be
asserted within the time specified for purely asynchronous operation, or it must be
asserted and remain stable during the sample window around the next falling edge of the
clock after
asserted and remain stable during the sample window around the next falling edge of the
clock after
DSACK
≈
is recognized. If
BERR
is not stable at this time, the MC68340 may
exhibit erratic behavior.
BERR
has priority over
DSACK
≈
. In this case, data may be
present on the bus, but it may not be valid. This sequence can be used by systems that
have memory error detection and correction logic and by external cache memories.
have memory error detection and correction logic and by external cache memories.
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Freescale Semiconductor, Inc.
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