B&B Electronics 232PCC2 User Manual
Documentation Number 232PCC23799 Manual
21
B&B Electronics Mfg Co Inc – 707 Dayton Rd - PO Box 1040 - Ottawa IL 61350 - Ph 815-433-5100 - Fax 815-433-5104
B&B Electronics Ltd – Westlink Commercial Park – Oranmore, Galway, Ireland – Ph +353-91-792444 – Fax +353-91-792445
Chapter 5: Hardware Information
The 232PCC2’s two asynchronous serial ports are implemented
using 2 standard 16C550 UARTs. Each of these UARTs requires 8
bytes of I/O space and when enabled which requires the 232PCC2
to be located on an even 16-byte (10H) boundary (e.g. 300H, 310H,
320H, etc.).
bytes of I/O space and when enabled which requires the 232PCC2
to be located on an even 16-byte (10H) boundary (e.g. 300H, 310H,
320H, etc.).
Each 16C550 UART contains 8 I/O registers. The last of these
registers, located at (Base address + 7), is referred to as the
'Scratchpad Register' and provides no functionality to the UART. In
place of this Scratchpad Register, the 232PCC2 implements an
interrupt status register which can be accessed at (Base address +
7) of any UART. The purpose of the interrupt status register is to
give the software programmer an easy way to inspect the interrupt
state of the entire 232PCC2 with a single input operation. The
format of the interrupt status register is shown below:
'Scratchpad Register' and provides no functionality to the UART. In
place of this Scratchpad Register, the 232PCC2 implements an
interrupt status register which can be accessed at (Base address +
7) of any UART. The purpose of the interrupt status register is to
give the software programmer an easy way to inspect the interrupt
state of the entire 232PCC2 with a single input operation. The
format of the interrupt status register is shown below:
When one or more UARTs have interrupts pending, the
associated bit(s) in the interrupt status register are set to logic 1.
When all the pending interrupts have been serviced for a specific
UART, its interrupt status bit will be cleared to logic 0 automatically.
When all the pending interrupts from all UARTs have been serviced,
the entire interrupt status register will return logic 0. The application
program should not exit its interrupt service routine until all pending
interrupts from all channels have been serviced (interrupt status
register = 0) or no additional interrupts will be received.
When all the pending interrupts have been serviced for a specific
UART, its interrupt status bit will be cleared to logic 0 automatically.
When all the pending interrupts from all UARTs have been serviced,
the entire interrupt status register will return logic 0. The application
program should not exit its interrupt service routine until all pending
interrupts from all channels have been serviced (interrupt status
register = 0) or no additional interrupts will be received.
If an application requires the UARTs' Scratchpad Registers, the
interrupt status register can be disabled. Disabling the interrupt
status register is supported by the 232PCC2 configuration software,
which is operating system dependent. Refer to the relevant
operating system installation section for specific usage of this
feature.
status register is supported by the 232PCC2 configuration software,
which is operating system dependent. Refer to the relevant
operating system installation section for specific usage of this
feature.
232PCC2 RS-232
Channel
Address Assignment
Channel A
Base Address + 0
Channel B
Base Address + 8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
Intr B Intr A