SMSC LAN1198 User Manual
LAN9118 Family Programmer Reference Guide
SMSC AN 12.12
27
Revision 1.0 (12-14-09)
APPLICATION NOTE
6 Transmit Packet Processing
Transmitting packets is a straightforward process compared with receiving packets; in that the host can
efficiently synchronize the entire transmit process with the application. In practice though, interrupts
are still needed for synchronizing to the time-dependant embedded applications.
efficiently synchronize the entire transmit process with the application. In practice though, interrupts
are still needed for synchronizing to the time-dependant embedded applications.
Memory Alignment Technology (MAT) in the LAN9118 family allows the driver to optimize the data flow
between packet data memory and the device FIFO by allowing the driver to always perform aligned,
efficient data transfers, regardless of the packet data organization in memory. This is achieved by
providing a descriptor along with the data, one for each transfer, called a Command Word that indicates
the true alignment of the packet, along with an indicator of the underlying hardware nature of the
transfer.
between packet data memory and the device FIFO by allowing the driver to always perform aligned,
efficient data transfers, regardless of the packet data organization in memory. This is achieved by
providing a descriptor along with the data, one for each transfer, called a Command Word that indicates
the true alignment of the packet, along with an indicator of the underlying hardware nature of the
transfer.
6.1 Transmit Data Transfer
At the heart of the transmit packet process, two DWORD values called TX_CMD_A and TX_CMD_B
command words are written into the device transmit data register (TX_DATA_FIFO), followed by the
packet buffer data. Host devices using Programmed IO (PIO) for data transfers work by copying packet
data in 4-byte increments aligned to 4-byte address boundaries. DMA-controllers generally transfer
data in 4-, 16- and 32-byte increments that are correspondingly aligned in memory . On the other hand,
the OS data buffers may begin on arbitrary byte boundaries, creating misaligned transfers with respect
to the physical addressing and caching of the CPU or DMA Controller. Memory Alignment Technology
(MAT) uses a description of the misalignment to allow the hardware to compensate for the misaligned
data buffers.
command words are written into the device transmit data register (TX_DATA_FIFO), followed by the
packet buffer data. Host devices using Programmed IO (PIO) for data transfers work by copying packet
data in 4-byte increments aligned to 4-byte address boundaries. DMA-controllers generally transfer
data in 4-, 16- and 32-byte increments that are correspondingly aligned in memory . On the other hand,
the OS data buffers may begin on arbitrary byte boundaries, creating misaligned transfers with respect
to the physical addressing and caching of the CPU or DMA Controller. Memory Alignment Technology
(MAT) uses a description of the misalignment to allow the hardware to compensate for the misaligned
data buffers.
Take a moment to notice that the transmit data FIFO register is aliased to 8 contiguous DWORD
locations. The purpose of this aliasing is to accommodate DMA controllers which transfer data in 16-
and 32-byte bursts. This is not meant to imply that misaligned data transfers need to write to
misaligned addresses within the device; that alignment is handled in the software construction of the
data transfer base address. Rather that the writer should be mindful that some CPUs and DMA
engines will generate extra, sequential addressing cycles to memory; use of the term “extra” is only
from the driver’s perspective. Phantom addressing cycles might be a more appropriate term, such as
when the DMA engine transfers a 32-byte burst of data to the device, creating 8 x DWORD accesses,
each on a unique, ascending DWORD boundary.
locations. The purpose of this aliasing is to accommodate DMA controllers which transfer data in 16-
and 32-byte bursts. This is not meant to imply that misaligned data transfers need to write to
misaligned addresses within the device; that alignment is handled in the software construction of the
data transfer base address. Rather that the writer should be mindful that some CPUs and DMA
engines will generate extra, sequential addressing cycles to memory; use of the term “extra” is only
from the driver’s perspective. Phantom addressing cycles might be a more appropriate term, such as
when the DMA engine transfers a 32-byte burst of data to the device, creating 8 x DWORD accesses,
each on a unique, ascending DWORD boundary.
6.2 Command Word Construction
The TX_CMD_A command word contains six fields of concern:
1. Buffer End Alignment is a 2-bit field which controls device behavior with a DMA controller. As
mentioned above, PIO transfers always use 4-byte alignment, which results in the packet data
buffer transfer occurring in a multiple of DWORD transfers; the last DWORD transfer may contain
pad bytes, depending upon the size of the transfer, modulo 4.
buffer transfer occurring in a multiple of DWORD transfers; the last DWORD transfer may contain
pad bytes, depending upon the size of the transfer, modulo 4.
In addition to PIO transfer, LAN9118 Family devices are designed to take advantage of the more
efficient data transfer modes afforded by the use of a DMA controller. When using DMA with the
device, burst transfers where the read/write access to the device is burst across 4 or 8 contiguous
DWORD addresses, the device’s aliasing of the TX Data FIFO register presents a simple memory
interface to the DMA controller. The setting of End Alignment causes the device to insert pad bytes
into the final transfer, filling the remainder of the 16- or 32-byte transfer, but without causing these
bytes to end up in the transmit data stream.
efficient data transfer modes afforded by the use of a DMA controller. When using DMA with the
device, burst transfers where the read/write access to the device is burst across 4 or 8 contiguous
DWORD addresses, the device’s aliasing of the TX Data FIFO register presents a simple memory
interface to the DMA controller. The setting of End Alignment causes the device to insert pad bytes
into the final transfer, filling the remainder of the 16- or 32-byte transfer, but without causing these
bytes to end up in the transmit data stream.
Data Start Offset is a 5-bit field which indicates to the device the number of bytes offset from the
aligned, base-address where the data actually begins. Table 4-2 shows how to construct the
Buffer End Alignment and Data Start Offset fields. In a 4-byte example, the data transfer begins
at physical address YYYY, with its lowest 2 address bits cleared (xx == 00b).
aligned, base-address where the data actually begins. Table 4-2 shows how to construct the
Buffer End Alignment and Data Start Offset fields. In a 4-byte example, the data transfer begins
at physical address YYYY, with its lowest 2 address bits cleared (xx == 00b).
First Segment is a 1-bit indication that the data transfer marks the beginning of a single packet.