PMC-Sierra PM5355 Leaflet
PMC-940402 (R5)
©1998 PMC-Sierra, Inc. October, 1998
PM5355
PMC-Sierra,Inc.
622 Mbit/s SATURN User Network Interface
S/UNI-622
FEATURES
• Monolithic SATURN
®
-compatible
SONET/SDH ATM User Network
Interface (UNI) for LAN, Public UNI, and
Public NNI connections.
Interface (UNI) for LAN, Public UNI, and
Public NNI connections.
• Implements the ATM Transmission
Convergence (TC) sublayer according to
ATM Forum specifications using the
SONET/SDH 622.08 Mbit/s and
155.52 Mbit/s formats.
ATM Forum specifications using the
SONET/SDH 622.08 Mbit/s and
155.52 Mbit/s formats.
• Also supports the SONET 51.84 Mbit/s
format.
• Processes all SONET/SDH UNI
overhead.
• Inserts and extracts ATM payloads using
ATM cell delineation.
• Provides a SCI-PHY™-compliant 50 MHz
synchronous 16-bit (4-cell deep) FIFO
buffers in both transmit and receive paths.
buffers in both transmit and receive paths.
• Compatible with ATM Forum UTOPIA
interface format, with support for multi-
PHY applications.
PHY applications.
• Provides access to section and line
datalinks and all additional overhead to
allow external processing for full
SONET/SDH Network-Node Interface
(NNI) compliance.
allow external processing for full
SONET/SDH Network-Node Interface
(NNI) compliance.
• Provides a generic 8-bit
microprocessor bus interface for
configuration, control, and status
monitoring.
configuration, control, and status
monitoring.
• Provides a standard 5-signal P1149.1
JTAG test port for boundary scan
board test purposes.
board test purposes.
• Provides TTL-compatible inputs and
outputs.
• Low power, +5 V CMOS technology.
• Packaged in a 208-pin, 28 mm by
28 mm slugged Plastic Quad Flat Pack
(PQFP) with 0.5 mm pin pitch.
(PQFP) with 0.5 mm pin pitch.
APPLICATIONS
• Workstations and Personal Computer
• LAN Switches and Hubs
• Routers
• Video Servers
• Backbones
• Broadband Switching Systems
• Test Equipment
• LAN Switches and Hubs
• Routers
• Video Servers
• Backbones
• Broadband Switching Systems
• Test Equipment
BLOCK DIAGRAM
D[
7
:0
]
A[
7
:0
]
AL
E
CSB
WRB
RDB
INT
B
Microprocessor
Interface
RS
T
B
Byte-
Interleaved
Mux
TPO
H
TPO
H
FP
FPIN
FPOS
PIN[7:0]
FPOUT
TSICLK
TSOUT
POUT[7:0]
OOF
PICLK
Receive
Section
O/H
Processor
T
SEN
RSICLK
RSIN
Transmit
Section
O/H
Processor
Parallel
Input/Output
Port
PO
P[
5
:0
]
PI
P[
3
:0
]
Transmit
ATM Cell
Processor
Path
Trace
Buffer
Byte-
Interleaved
Demux
Receive ConCat
Processor
Transmit ConCat
Processor
Transmit Path
O/H Processor
Receive Path
O/H Processor
Receive
Line O/H
Processor
Transmit
Line O/H
Line O/H
Processor
Section
Trace
Buffer
Transport
O/H
Insert
Line Side
Interface
LO
S
LOF
RSDCL
K, RO
WCL
K
RSD, RSO
W
, RSUC
Receive
ATM Cell
Processor
JTAG Test
Access Port
TD
O
TD
I
TC
K
TR
ST
B
TM
S
Transmit
ATM 4-Cell
FIFO
Receive
ATM 4-Cell
FIFO
RSOC
RDAT[15:0]
RXPRTY[1:0]
RCA
TXPRTY[1:0]
TSOC
TDAT[15:0]
TDAT[15:0]
RRDENB
RFCLK
TCA
TWRENB
TFCLK
TWRENB
TFCLK
Drop
Side
Interface
RCP
RGF
C
LC
D
LA
IS
L
RDI
RL
DCL
K
RL
D, RL
OW
RT
OH
[4:1
]
RT
OHF
P
RT
O
HCL
K
OHF
P
RP
O
H
RPOHF
P
RPO
HCL
K
LO
P
PAI
S
PRDI
GRO
C
LK
Transport
O/H
Extract
TC
P
TG
FC
XO
FF
TPA
IS
T
P
RDI
T
P
OHCL
K
TPO
H
EN
TC
L
K
TF
P
GT
OCL
K
TT
O
H
EN
T
T
O
H
[4:1
]
TT
O
H
F
P
T
T
O
HCL
K
T
L
RDI
T
L
DCL
K
TL
D
, T
L
O
W
TL
AI
S
TSD
C
L
K,
TO
W
C
LK
TSD
, TS
O
W
, TSU
C
Path
O/H
Insert
Path O/H
Extract