Nxp Semiconductors UM10310 User Manual
UM10310_1
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 01 — 1 December 2008
40 of 139
NXP Semiconductors
UM10310
P89LPC9321 User manual
7.1 Mode 0
Putting either Timer into Mode 0 makes it look like an 8048 Timer, which is an 8-bit
Counter with a divide-by-32 prescaler.
Counter with a divide-by-32 prescaler.
shows Mode 0 operation.
In this mode, the Timer register is configured as a 13-bit register. As the count rolls over
from all 1s to all 0s, it sets the Timer interrupt flag TFn. The count input is enabled to the
Timer when TRn = 1 and either TnGATE = 0 or INTn = 1. (Setting TnGATE = 1 allows the
Timer to be controlled by external input INTn, to facilitate pulse width measurements).
TRn is a control bit in the Special Function Register TCON (
from all 1s to all 0s, it sets the Timer interrupt flag TFn. The count input is enabled to the
Timer when TRn = 1 and either TnGATE = 0 or INTn = 1. (Setting TnGATE = 1 allows the
Timer to be controlled by external input INTn, to facilitate pulse width measurements).
TRn is a control bit in the Special Function Register TCON (
). The TnGATE bit is
in the TMOD register.
The 13-bit register consists of all 8 bits of THn and the lower 5 bits of TLn. The upper 3
bits of TLn are indeterminate and should be ignored. Setting the run flag (TRn) does not
clear the registers.
bits of TLn are indeterminate and should be ignored. Setting the run flag (TRn) does not
clear the registers.
. There are two
different GATE bits, one for Timer 1 (TMOD.7) and one for Timer 0 (TMOD.3).
7.2 Mode 1
Mode 1 is the same as Mode 0, except that all 16 bits of the timer register (THn and TLn)
are used. See
are used. See
Table 26.
Timer/Counter Auxiliary Mode register (TAMOD - address 8Fh) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
--
-
-
T1M2
-
-
-
T0M2
Reset
x
x
x
0
x
x
x
0
Table 27.
Timer/Counter Auxiliary Mode register (TAMOD - address 8Fh) bit description
Bit Symbol
Description
0
T0M2
Mode Select for Timer 0. These bits are used with the T0M2 bit in the TAMOD register to determine the
Timer 0 mode (see
Timer 0 mode (see
1:3 - reserved
4
T1M2
Mode Select for Timer 1. These bits are used with the T1M2 bit in the TAMOD register to determine the
Timer 1 mode (see
Timer 1 mode (see
The following timer modes are selected by timer mode bits TnM[2:0]:
000 — 8048 Timer ‘TLn’ serves as 5-bit prescaler. (Mode 0)
001 — 16-bit Timer/Counter ‘THn’ and ‘TLn’ are cascaded; there is no prescaler.(Mode 1)
010 — 8-bit auto-reload Timer/Counter. THn holds a value which is loaded into TLn when it overflows.
(Mode 2)
(Mode 2)
011 — Timer 0 is a dual 8-bit Timer/Counter in this mode. TL0 is an 8-bit Timer/Counter controlled by the
standard Timer 0 control bits. TH0 is an 8-bit timer only, controlled by the Timer 1 control bits (see text).
Timer 1 in this mode is stopped. (Mode 3)
standard Timer 0 control bits. TH0 is an 8-bit timer only, controlled by the Timer 1 control bits (see text).
Timer 1 in this mode is stopped. (Mode 3)
100 — Reserved. User must not configure to this mode.
101 — Reserved. User must not configure to this mode.
110 — PWM mode (see
111 — Reserved. User must not configure to this mode.
5:7 -
reserved