Nxp Semiconductors UM10310 User Manual
UM10310_1
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 01 — 1 December 2008
99 of 139
NXP Semiconductors
UM10310
P89LPC9321 User manual
If PGA is enabled, it will consume power. Power can be reduced by disabling the PGA.
PGA can be disabled via clearing ENPGAx bit.
PGA can be disabled via clearing ENPGAx bit.
In Power-down mode or Total Power-down mode, PGA does not function.
Table 85.
PGA trim register
Register bits
Contains
PGAxTRIM2X4X[3:0]
trim value for 2x gain value
PGAxTRIM2X4X[7:4]
trim value for 4x gain value
PGAxTRIM8X16X[3:0]
trim value for 8x gain value
PGAxTRIM8X16X[7:4]
trim value for16x gain value
Table 86.
PGA1 Control register (PGACON1 - address FFE1h) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
ENPGA1
PGASEL11
PGASEL10
PGATRIM1
-
-
PGAG11
PGAG10
Reset
0
0
0
0
0
0
0
0
Table 87.
PGA1 Control register (PGACON1 - address FFE1h) bit description
Bit
Symbol
Description
1:0
PGAG11, PGAG10
PGA Gain selection bits.
00 : Gain = 2
01 : Gain = 4
10 : Gain = 8
11 : Gain = 16
3:2
-
reserved
4
PGATRIM1
If set, PGA1 is grounded. If cleared, normal operation mode.
6:5
PGASEL11,
PGASEL10
PGASEL10
PGA input channel selection
00 : CIN2B using PGA
01 : CIN2A using PGA
10 : CIN1B using PGA
11 : CIN1A using PGA
7
ENPGA1
PGA1 enable. If set, enable PGA1. If cleared, disable PGA1.
Table 88.
PGA1 Control register B (PGACON1B - address FFE4h) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
-
-
-
-
-
-
-
PGAENOF
F1
F1
Reset
0
0
0
0
0
0
0
0
Table 89.
PGA1 Control register B (PGACON1B - address FFE4h) bit description
Bit
Symbol
Description
0
PGAENOFF1
PGA offset voltage enable bit. When set, enable the offset voltage on the PGA.
1:7
-
Reserved