Samsung S3C2410A User Manual
ARM920T PROCESSOR
CLOCK MODES
5-1
Appendix 5
CLOCK MODES
OVERVIEW
The ARM920T has two functional clock inputs, BCLK and FCLK. Internally, the ARM920T is clocked by GCLK,
which can be seen on the CPCLK output as shown in Figure 5-1. GCLK can be sourced from either BCLK or FCLK
depending on the clocking mode, selected using nF bit and iA bit in CP15 register 1 (see Register 1: Control register
on page 2-10). The three clocking modes are FastBus, synchronous and asynchronous.
which can be seen on the CPCLK output as shown in Figure 5-1. GCLK can be sourced from either BCLK or FCLK
depending on the clocking mode, selected using nF bit and iA bit in CP15 register 1 (see Register 1: Control register
on page 2-10). The three clocking modes are FastBus, synchronous and asynchronous.
The ARM920T is a static design and both clocks can be stopped indefinitely without loss of state. From Figure 5-1
it can be seen that some of the ARM920T macrocell signals will have timing specified with relation to GCLK, which
can be either FCLK or BCLK depending on the clocking mode
it can be seen that some of the ARM920T macrocell signals will have timing specified with relation to GCLK, which
can be either FCLK or BCLK depending on the clocking mode
AMBA
bus
interface
nF, iA
FCLK
BCLK
GCLK
Rest of ARM920T
CPCLK
ARM920T I/O
ASB
Figure 5-1. ARM920T Clocking