Nxp Semiconductors UM10237 User Manual

UM10237_2

© NXP B.V. 2008. All rights reserved.

The LCD_LE register controls the enabling of line-end signal LCDLE. When enabled, a 
positive pulse, four LCDCLK periods wide, is output on LCDLE after a programmable 
delay, LED, from the last pixel of each display line. If the line-end signal is disabled it is 
held permanently LOW.

The contents of the LCD_LE register are described in 

10:6

ACB

AC bias pin frequency.

The AC bias pin frequency is only applicable to STN displays. 
These require the pixel voltage polarity to periodically reverse to 
prevent damage caused by DC charge accumulation. Program 
this field with the required value minus one to apply the number 
of line clocks between each toggle of the AC bias pin, 
LCDENAB. This field has no effect if the LCD is operating in TFT 
mode, when the LCDENAB pin is used as a data enable signal.

0x0

5

CLKSEL

Clock Select.

This bit controls the selection of the source for LCDCLK.

0 = the clock source for the LCD block is CCLK.

1 = the clock source for the LCD block is LCDDCLK.

0x0

4:0

PCD_LO

Lower five bits of panel clock divisor.

The ten-bit PCD field, comprising PCD_HI (bits 31:27 of this 
register) and PCD_LO, is used to derive the LCD panel clock 
frequency LCDDCLK from the input clock, LCDDCLK = 
LCDCLK/(PCD+2).

For monochrome STN displays with a 4 or 8-bit interface, the 
panel clock is a factor of four and eight down from the actual 
individual pixel clock rate. For color STN displays, 22/3 pixels 
are output per LCDDCLK cycle, so the panel clock is 0.375 times 
the pixel rate.

For TFT displays, the pixel clock divider can be bypassed by 
setting the BCD bit in this register.

 data path latency forces some restrictions on the usable 

minimum values for the panel clock divider in STN modes:

Single panel color mode, PCD = 1 (LCDDCLK = LCDCLK/3).

Dual panel color mode, PCD = 4 (LCDDCLK = LCDCLK/6).

Single panel monochrome 4-bit interface mode, PCD = 
2(LCDDCLK = LCDCLK/4).

Dual panel monochrome 4-bit interface mode and single panel 
monochrome 8-bit interface mode, PCD = 6(LCDDCLK = 
LCDCLK/8).

Dual panel monochrome 8-bit interface mode, PCD = 
14(LCDDCLK = LCDCLK/16).

0x0