Nxp Semiconductors UM10237 User Manual

UM10237_2

© NXP B.V. 2008. All rights reserved.

 

In the slave transmitter mode, a number of data bytes are transmitted to a master receiver 
(see 

). Data transfer is initialized as in the slave receiver mode. When 

I2ADR and I2CON have been initialized, the I

2

C block waits until it is addressed by its own 

slave address followed by the data direction bit which must be “1” (R) for the I

2

C block to 

operate in the slave transmitter mode. After its own slave address and the R bit have been 
received, the serial interrupt flag (SI) is set and a valid status code can be read from 
I2STAT. This status code is used to vector to a state service routine, and the appropriate 
action to be taken for each of these status codes is detailed in 

. The slave 

transmitter mode may also be entered if arbitration is lost while the I

2

C block is in the 

master mode (see state 0xB0).

If the AA bit is reset during a transfer, the I

2

C block will transmit the last byte of the transfer 

and enter state 0xC0 or 0xC8. The I

2

C block is switched to the not addressed slave mode 

and will ignore the master receiver if it continues the transfer. Thus the master receiver 
receives all 1s as serial data. While AA is reset, the I

2

C block does not respond to its own 

slave address or a general call address. However, the I

2

C bus is still monitored, and 

address recognition may be resumed at any time by setting AA. This means that the AA 
bit may be used to temporarily isolate the I

2

C block from the I

2

C bus. 

DATA

A

A

R

SLA

S

P OR S

A

A

B0H

A8H

C0H

C8H

last data byte
transmitted. Switched
to Not Addressed
Slave (AA bit in
I2CON = “0”)

arbitration lost as
Master and
addressed as Slave

reception of the own
Slave address and
one or more Data
bytes all are
acknowledged

from Master to Slave

from Slave to Master

any number of data bytes and their associated
Acknowledge bits

n

this number (contained in I2STA) corresponds to a defined state of
the I

2

C bus

A

DATA

B8H

ALL ONES

A

DATA

P OR S