Renesas M306V8T-EPB User Manual
M306V8T-EPB User’s Manual
4. Hardware Specifications
REJ10J0777-0100 Rev.1.00 2005.08.01
Page 72 of 90
IMPORTANT
Notes on Pullup Control:
Because this product emulates some I/O ports (P0 to P5, P10), you can not pullup ports P0 to P5 by the pullup
control registers, Install the included resistor arrays (51 kΩ) as necessary.
control registers, Install the included resistor arrays (51 kΩ) as necessary.
The initial value of pullup control register 1 PUR1 of this product is different from that of an actual MCU.
When a Vcc level is input to pin CNVss, the value of an actual MCU is “02h” (bit 1 PU11 is “1”), while that of
this product is “00h”.
When a Vcc level is input to pin CNVss, the value of an actual MCU is “02h” (bit 1 PU11 is “1”), while that of
this product is “00h”.
Note on Setting "1" to Protect Bit 2 (PCR2) with Sub Clock:
When the CPU clock is set to the sub-clock (low-speed mode or low power dissipation mode), even if you
enable the PRC2 bit, writing to the register protected by the PRC2 bit (PD9, address 0362h and 0366h registers)
cannot be done properly. When you enable the PRC2 bit and write to the register protected by the PRC2 (PD9,
address 0362h and 0366h registers), do not set the CPU clock to the sub-clock.
enable the PRC2 bit, writing to the register protected by the PRC2 bit (PD9, address 0362h and 0366h registers)
cannot be done properly. When you enable the PRC2 bit and write to the register protected by the PRC2 (PD9,
address 0362h and 0366h registers), do not set the CPU clock to the sub-clock.
Note on Setting "1" to Protect Bit 2 (PRC2) in Division by 2 Mode:
Under the following conditions, even if you enable the PRC2 bit, writing to the register protected by the PRC2
bit (PD9, address 0362h and 0366h registers) cannot be done properly.
bit (PD9, address 0362h and 0366h registers) cannot be done properly.
(1) Between when stop mode is released and when a hardware reset is executed
(2) Between when low power dissipation mode is enabled and when a hardware reset is executed
(2) Between when low power dissipation mode is enabled and when a hardware reset is executed
Therefore, if the condition (1) or (2) applies, when you enable the PRC2 bit and write to the register protected
by the PRC2 (PD9, address 0362h and 0366h registers), set the CPU clock neither to the main clock in division
by 2 mode nor to the on-chip oscillator clock in division by 2 mode.
by the PRC2 (PD9, address 0362h and 0366h registers), set the CPU clock neither to the main clock in division
by 2 mode nor to the on-chip oscillator clock in division by 2 mode.
Note on the Input Thresholds for the Pins P1_5/D13/INT3, P1_6/D14/INT4 and P1_7/D15/INT5
With this product, regarding pins P1_5/D13/INT3, P1_6/D14/INT4 and P1_7/D15/INT5, a device which port or
data bus inputs to and a device which INT interrupt inputs to are different as follows:
data bus inputs to and a device which INT interrupt inputs to are different as follows:
Device which port or data bus inputs to: Port emulation FPGA (input level: TTL)
Device which INT interrupt inputs to: Evaluation MCU for emulating peripheral functions (input level:
CMOS Schmidt)
Device which INT interrupt inputs to: Evaluation MCU for emulating peripheral functions (input level:
CMOS Schmidt)
Therefore, the port input level can be read as “H” immediately after an INT interrupt (falling), and the port input
level can be read as “H” immediately before an INT interrupt (rising).
level can be read as “H” immediately before an INT interrupt (rising).
Note on Final Evaluation:
Be sure to evaluate your system with an evaluation MCU. Before starting mask production, evaluate your
system and make final confirmation with a CS (Commercial Sample) version MCU.
system and make final confirmation with a CS (Commercial Sample) version MCU.