Renesas 4514 User Manual
APPLICATION
2.3 Timers
2-27
4513/4514 Group User’s Manual
2.3.2 Related registers
(1)
Interrupt control register V1
The timer 1 interrupt enable bit is assigned to bit 2, and the timer 2 interrupt enable bit is assigned
to bit 3.
Set the contents of this register through register A with the TV1A instruction. The TAV1 instruction
can be used to transfer the contents of register V1 to register A.
Table 2.3.1 shows the interrupt control register V1.
The timer 1 interrupt enable bit is assigned to bit 2, and the timer 2 interrupt enable bit is assigned
to bit 3.
Set the contents of this register through register A with the TV1A instruction. The TAV1 instruction
can be used to transfer the contents of register V1 to register A.
Table 2.3.1 shows the interrupt control register V1.
Table 2.3.1 Interrupt control register V1
Interrupt control register V1
at reset : 0000
2
at RAM back-up : 0000
2
R/W
Interrupt disabled (SNZT2 instruction is valid)
Interrupt enabled (SNZT2 instruction is invalid)
Interrupt disabled (SNZT1 instruction is valid)
Interrupt enabled (SNZT1 instruction is invalid)
Interrupt disabled (SNZ1 instruction is valid)
Interrupt enabled (SNZ1 instruction is invalid)
Interrupt disabled (SNZ0 instruction is valid)
Interrupt enabled (SNZ0 instruction is invalid)
Timer 2 interrupt enable bit
Timer 1 interrupt enable bit
External 1 interrupt enable bit
External 0 interrupt enable bit
V1
3
V1
2
V1
1
V1
0
0
1
0
1
0
1
0
1
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: When timer is used, V1
1
and V1
0
are not used.
(2)
Interrupt control register V2
The timer 3 interrupt enable bit is assigned to bit 0, and the timer 4 interrupt enable bit is assigned
to bit 1.
Set the contents of this register through register A with the TV2A instruction. The TAV2 instruction
can be used to transfer the contents of register V2 to register A.
Table 2.3.2 shows the interrupt control register V2.
The timer 3 interrupt enable bit is assigned to bit 0, and the timer 4 interrupt enable bit is assigned
to bit 1.
Set the contents of this register through register A with the TV2A instruction. The TAV2 instruction
can be used to transfer the contents of register V2 to register A.
Table 2.3.2 shows the interrupt control register V2.
Table 2.3.2 Interrupt control register V2
Interrupt control register V2
at reset : 0000
2
at RAM back-up : 0000
2
R/W
Interrupt disabled (SNZSI instruction is valid)
Interrupt enabled (SNZSI instruction is invalid)
Interrupt disabled (SNZAD instruction is valid)
Interrupt enabled (SNZAD instruction is invalid)
Interrupt disabled (SNZT4 instruction is valid)
Interrupt enabled (SNZT4 instruction is invalid)
Interrupt disabled (SNZT3 instruction is valid)
Interrupt enabled (SNZT3 instruction is invalid)
Serial I/O interrupt enable bit
A-D interrupt enable bit
Timer 4 interrupt enable bit
Timer 3 interrupt enable bit
V2
3
V2
2
V2
1
V2
0
0
1
0
1
0
1
0
1
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: When timer is used, V2
2
and V2
3
are not used.