Renesas 4514 User Manual
4513/4514 Group User’s Manual
APPENDIX
3-21
3.3 List of precautions
3.3 List of precautions
➀
Noise and latch-up prevention
Connect a capacitor on the following condition to prevent noise
and latch-up;
• connect a bypass capacitor (approx. 0.1
µ
F) between pins V
DD
and V
SS
at the shortest distance,
• equalize its wiring in width and length, and
• use relatively thick wire.
In the One Time PROM version, CNV
SS
pin is also used as V
PP
pin. Accordingly, when using this pin, connect this pin to V
SS
through a resistor about 5 k
Ω
in series at the shortest distance.
➁
Prescaler
Stop the prescaler operation to change its frequency dividing ra-
tio.
➂
Timer count source
Stop timer 1, 2, 3, or 4 counting to change its count source.
➃
Reading the count value
Stop timer 1, 2, 3, or 4 counting and then execute the TAB1,
TAB2, TAB3, or TAB4 instruction to read its data.
➄
Writing to reload registers R1 and R3
When writing data to reload registers R1 or R3 while timer 1 or
timer 3 is operating, avoid a timing when timer 1 or timer 3
underflows.
➅
P3
0
/INT0 pin
When the interrupt valid waveform of the P3
0
/INT0 pin is
changed with the bit 2 of register I1 in software, be careful about
the following notes.
• Clear the bit 0 of register V1 to “0” before the interrupt valid wave-
form of P3
0
/INT0 pin is changed with the bit 2 of register I1 (refer
to Figure 44
➀
).
• Depending on the input state of the P3
0
/INT0 pin, the external 0
interrupt request flag (EXF0) may be set when the interrupt valid
waveform is changed. Accordingly, clear bit 2 of register I1, and
execute the SNZ0 instruction to clear the EXF0 flag after execut-
ing at least one instruction (refer to Figure 44
➁
)
Fig. 45 External 1 interrupt program example
➇
One Time PROM version
The operating power voltage of the One Time PROM version is
2.5 V to 5.5 V.
➈
Multifunction
The input of D
6
, D
7
, P2
0
–P2
2
, I/O of P3
0
and P3
1
, input of CMP0-,
CMP0+, CMP1-, CMP1+, and I/O of P4
0
–P4
3
can be used even
when CNTR0, CNTR1, S
CK
, S
OUT
, S
IN
, INT0, INT1, A
IN0
–A
IN3
and A
IN4
–A
IN7
are selected.
➆
P3
1
/INT1 pin
When the interrupt valid waveform of P3
1
/INT1 pin is changed
with the bit 2 of register I2 in software, be careful about the fol-
lowing notes.
• Clear the bit 1 of register V1 to “0” before the interrupt valid wave-
form of P3
1
/INT1 pin is changed with the bit 2 of register I2 (refer
to Figure 45
➂
).
• Depending on the input state of the P3
1
/INT1 pin, the external 1
interrupt request flag (EXF1) may be set when the interrupt valid
waveform is changed. Accordingly, clear bit 2 of register I2 and
execute the SNZ1 instruction to clear the EXF1 flag after execut-
ing at least one instruction (refer to Figure 45
➃
).
LA
8
; (
✕✕
0
✕
2
)
TV1A
; The SNZ1 instruction is valid ...........
➂
LA
8
TI2A
; Change of the interrupt valid waveform
NOP
...........................................................
➃
SNZ1
; The SNZ1 instruction is executed
NOP
✕
: this bit is not related to the setting of INT1.
...
...
LA
4
; (
✕✕✕
0
2
)
TV1A
; The SNZ0 instruction is valid ...........
➀
LA
4
;
TI1A
; Interrupt valid waveform is changed
NOP
...........................................................
➁
SNZ0
; The SNZ0 instruction is executed
NOP
✕
: this bit is not related to the setting of INT0 pin.
...
...
Fig. 44 External 0 interrupt program example