Focus Enhancements FS456 Data Sheet
FS453/4 AND FS455/6
DATA SHEET: HARDWARE REFERENCE
7.3 Switching Characteristics
Parameter Conditions
Min
Typ
(b)
Max Unit
Clocks
f
f
CKIN
TV Encoder Reference Clock Frequency
27.0
MHz
f
XTOL
TV Reference Clock Frequency Tolerance
30
50
(c)
ppm
t
PWHT
TV Reference Clock Pulse Width, HIGH
15.0
ns
t
PWLT
TV Reference Clock Pulse Width, LOW
15.0
ns
f
CLKIN
Pixel Clock Frequency
40/60 duty cycle
18.0
150.0 MHz
f
CORE
Scaler Core Frequency
(d)
75.0
MHz
f
GCKO
GCC Clock Output Frequency
(a,e,f)
GTL, 2.5V and
3.3V scalable
3.3V scalable
0.78125 150.0
MHz
f
GCKO
GCC Clock Output Frequency
(e,f)
1.8V scalable
0.78125
120.0
MHz
f
GCKO
GCC Clock Output Frequency
(e,f)
1.5V scalable
0.78125
85.0
MHz
t
JIT-GCK
GCC Clock Output Jitter (peak-to-peak)
over a cycle
-250
250
ps
DC
GCK
Duty Cycle
150 MHz
40
60
%
f
PLLIN
PLL Input Clock Frequency
100
1000
kHz
M
PLL Numerator (integer value)
250
3000
N/A
f
PLLOUT
PLL Output Clock Frequency
100
300
MHz
Reset Assert
fCKIN cycles on RESET_L to reset
16
Clocks
Digital Pixel Input Port
t
t
PDH
Pixel Clock 0 to Data/Control Hold Time
V
REF
= 0.75V,
1.5V signaling.
0
ns
t
PDH
Pixel Clock 1 to Data/Control Hold Time
V
REF
= 0.75V,
1.5V signaling.
0
ns
t
PSU
Pixel Clock 0 to Data/Control Setup Time
V
REF
= 0.75V,
1.5V signaling.
1.2
ns
t
PSU
Pixel Clock 1 to Data/Control Setup Time
V
REF
= 0.75V,
1.5V signaling.
1.2 ns
Serial Interface
t
t
DAL
SCL Pulse Width, LOW
1.3
µs
t
DAH
SCL Pulse Width, HIGH
0.6
µs
t
STAH
SDA Start Hold Time
0.6
µs
t
STASU
SCL to SDA Setup Time (Stop)
0.6
µs
t
STOSU
SCL to SDA Setup Time (Start)
0.6
µs
t
BUFF
SDA Stop Hold Time Setup
1.3
µs
t
DSU
SDA to SCL Data Setup Time
100
ns
t
DHO
SDA to SCL Data Hold Time
0
ns
Table 8: Switching Characteristics
Notes:
(a) GTL outputs are open drain and are specified with 25 ohm terminations from 1.1 to 1.5 volts and a 15 pF load.
(b) Values shown in Typ column are typical for VDD33 = +3.3V, VDD18 = +1.8V, and TA = 25°C
(c) TV subcarrier acceptance band is
(b) Values shown in Typ column are typical for VDD33 = +3.3V, VDD18 = +1.8V, and TA = 25°C
(c) TV subcarrier acceptance band is
± 300 Hz.
(d) Scaler Core Frequency = VCO Frequency/PLL_IP
(e) GCC Output Frequency = VCO Frequency/PLL_EP
(f) Scalable (1.5 to 3.3V) LVTTL outputs are specified with a 15 pF load.
(e) GCC Output Frequency = VCO Frequency/PLL_EP
(f) Scalable (1.5 to 3.3V) LVTTL outputs are specified with a 15 pF load.
JANUARY, 2005, VERSION 3.0
27
COPYRIGHT
©2003-4 FOCUS ENHANCEMENTS, INC.
FOCUS Enhancements Semiconductor