Focus Enhancements FS456 Data Sheet
FS453/4 AND FS455/6
DATA SHEET: HARDWARE REFERENCE
graphics controller’s digital video data. The timing of the variable pixel clock is critical; any disturbances
to this signal will translate directly into noise on the video output.
The best method to stabilize the variable pixel clock signal is to source terminate the signal with a load
that matches the impedance of the signal trace. The simplest transmission line termination is a series 33
Ohm SMD resistor placed as close to the source pin on the FS453 as possible. This works well as long
as the signal only has one destination and does not change layers through vias.
Avoid passing the clock signal from layer to layer through vias. Each time a trace goes through a via, a
reflection inducing impedance mismatch occurs at the via, and a completely different impedance will be
present on the new layer. This makes proper termination of the clock signal nearly impossible.
Geometry variations and sudden trace direction changes can also create impedance mismatches.
Therefore, clock traces should maintain constant widths and have gradual/rounded direction changes.
For optimal results, match the impedance of the series termination resistor (nominally estimated at 33
Ohms) to the characteristic impedance of the trace. Use the URL link,
to this signal will translate directly into noise on the video output.
The best method to stabilize the variable pixel clock signal is to source terminate the signal with a load
that matches the impedance of the signal trace. The simplest transmission line termination is a series 33
Ohm SMD resistor placed as close to the source pin on the FS453 as possible. This works well as long
as the signal only has one destination and does not change layers through vias.
Avoid passing the clock signal from layer to layer through vias. Each time a trace goes through a via, a
reflection inducing impedance mismatch occurs at the via, and a completely different impedance will be
present on the new layer. This makes proper termination of the clock signal nearly impossible.
Geometry variations and sudden trace direction changes can also create impedance mismatches.
Therefore, clock traces should maintain constant widths and have gradual/rounded direction changes.
For optimal results, match the impedance of the series termination resistor (nominally estimated at 33
Ohms) to the characteristic impedance of the trace. Use the URL link,
to locate an online calculator that can help define the characteristic impedance of a trace on a PCB.
Maximum power transfer and minimum reflection occur when the load resistor equals the trace
impedance.
Also be careful to prevent coupling between the pixel clock from the FS453 and the pixel clock (or clocks)
that return from the graphics controller. All graphics controllers have internal Phase Locked Loops (which
generate output clocks based on input clocks). The CLKIN_N & CLKIN_P outputs from a graphics
controller are derived from the CLKOUT input from the FS453. Coupling from CLKOUT to CLKIN_N or
CLKIN_P will cause positive feedback (and stability problems) for the graphics controller. Keep CLKOUT
separated from CLKIN_N and CLKIN_P to prevent this from happening.
Maximum power transfer and minimum reflection occur when the load resistor equals the trace
impedance.
Also be careful to prevent coupling between the pixel clock from the FS453 and the pixel clock (or clocks)
that return from the graphics controller. All graphics controllers have internal Phase Locked Loops (which
generate output clocks based on input clocks). The CLKIN_N & CLKIN_P outputs from a graphics
controller are derived from the CLKOUT input from the FS453. Coupling from CLKOUT to CLKIN_N or
CLKIN_P will cause positive feedback (and stability problems) for the graphics controller. Keep CLKOUT
separated from CLKIN_N and CLKIN_P to prevent this from happening.
9.4.3 Pixel Clock Mode
Depending on the architecture and configuration of the graphics controller, the FS453 may use different
clock mode settings. In all these modes HSync, VSync and the pixel data must meet the setup and hold
time requirements (see Section 7.2 of the Hardware Reference, Switching Characteristics, Digital Input
Port) with respect to pixel clock.
The FS453 operates as an integral piece of the computer graphics control circuit. The FS453 receives a
digital video signal directly from the resident Graphics Controller Chip (GCC) and shares operating
information with the GCC. There are two possible modes in which the FS453 can interface with a GCC:
Pseudo-master Mode and Slave Mode.
clock mode settings. In all these modes HSync, VSync and the pixel data must meet the setup and hold
time requirements (see Section 7.2 of the Hardware Reference, Switching Characteristics, Digital Input
Port) with respect to pixel clock.
The FS453 operates as an integral piece of the computer graphics control circuit. The FS453 receives a
digital video signal directly from the resident Graphics Controller Chip (GCC) and shares operating
information with the GCC. There are two possible modes in which the FS453 can interface with a GCC:
Pseudo-master Mode and Slave Mode.
JANUARY, 2005, VERSION 3.0
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©2003-4 FOCUS ENHANCEMENTS, INC.
FOCUS Enhancements Semiconductor