Texas Instruments TMS380C26 User Manual
TMS380C26
NETWORK COMMPROCESSOR
SPWS010A–APRIL 1992–REVISED MARCH 1993
POST OFFICE BOX 1443
•
HOUSTON, TEXAS
77251–1443
Copyright
1993, Texas Instruments Incorporated
1
•
IEEE 802.5 and IBM Token-Ring Network
Compatible
Compatible
•
IEEE 802.3 and Blue Book Ethernet
Network Compatible
Network Compatible
•
Pin and Software Compatible With the
TMS380C16
TMS380C16
•
Configurable Network Type and Speed:
– Selectable by Host Software Control
– Selectable by Host Software Control
(Adapter Control Register)
– Selectable by Network Front-End
– Readable from Host (Adapter Control
– Readable from Host (Adapter Control
Register)
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Token-Ring Features
– 16- or 4-Megabit-per-Second Data Rates
– Supports up to 18K-Byte Frame Size
– 16- or 4-Megabit-per-Second Data Rates
– Supports up to 18K-Byte Frame Size
(16 Mbps Operation Only)
– Supports Universal and Local Network
Addressing
– Early Token Release Option (16 Mbps
Operation Only)
– Compatible With the TMS38054
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Ethernet Features
– 10-Megabit-per-Second Data Rate
– Compatible With Most Ethernet Serial
– 10-Megabit-per-Second Data Rate
– Compatible With Most Ethernet Serial
Network Interface Devices
– Full Duplex Ethernet Operation Allows
Network Speed Self-test
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Expandable Local LAN Subsystem Memory
Space up to 2 Megabytes
Space up to 2 Megabytes
•
Supports Multicast Addressing of Network
Group Addresses Through Hashing
Group Addresses Through Hashing
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Glueless Interface to DRAMs
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High-Performance 16-Bit CPU for
Communications Protocol Processing
Communications Protocol Processing
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Up to 8 Megabyte-per-Second High-Speed
Bus Master DMA Interface
Bus Master DMA Interface
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Low-Cost Host-Slave I/O Interface Option
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Up to 32-Bit Host Address Bus
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Selectable Host System Bus Options
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80x8x or 68xxx-Type Bus and Memory
Organization
– 8- or 16-Bit Data Bus on 80x8x Buses
– Optional Parity Checking
Organization
– 8- or 16-Bit Data Bus on 80x8x Buses
– Optional Parity Checking
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Dual-Port DMA and Direct I/O Transfers to
Host Bus
Host Bus
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Specification for External Adapter-Bus
Devices (SEADs) Supports External
Hardware Interface for User-Defined
External Logic
Devices (SEADs) Supports External
Hardware Interface for User-Defined
External Logic
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Enhanced Address Copy Option (EACO)
Interface Supports External Address
Checking Logic for Bridging or External
Custom Applications
Interface Supports External Address
Checking Logic for Bridging or External
Custom Applications
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Support for Module High-Impedance
In-Circuit Testing
In-Circuit Testing
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Built-in Real-Time Error Detection
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Bring-Up and Self-Test Diagnostics With
Loopback
Loopback
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Automatic Frame Buffer Management
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Slow-Clock Low-Power Mode
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Single 5-V Supply
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1-
µ
m CMOS Technology
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250 mA Typical Latch-Up Immunity at 25
°
C
•
ESD Protection Exceeds 2,000 V
•
132-Pin JEDEC Plastic Quad Flat Package
(PQ Suffix)
(PQ Suffix)
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Operating Temperature Range
0
0
°
C to 70
°
C
network commprocessor applications diagram
TMS380C26
Attached
System
Bus
LAN Subsystem
Memory
Token Ring or
Ethernet Physical
Layer Circuitry
Transmit
Receive
To
Network
Network
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.