Motorola MVME2600 User Manual
Programming Considerations
http://www.motorola.com/computer/literature
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Endian Issues
The MVME2603/2604 supports both little-endian (for example,
Windows NT) and big-endian (for example, AIX) software. The PowerPC
processor and the VMEbus are inherently big-endian, while the PCI bus is
inherently little-endian. The following sections summarize how the
MVME2603/2604 handles software and hardware differences in big- and
little-endian operations. For further details on endian considerations, refer
to the MVME2600 Series Single Board Computer Programmer’s
Reference Guide, listed in
Windows NT) and big-endian (for example, AIX) software. The PowerPC
processor and the VMEbus are inherently big-endian, while the PCI bus is
inherently little-endian. The following sections summarize how the
MVME2603/2604 handles software and hardware differences in big- and
little-endian operations. For further details on endian considerations, refer
to the MVME2600 Series Single Board Computer Programmer’s
Reference Guide, listed in
Processor/Memory Domain
The MPC603/604 processor can operate in both big-endian and
little-endian mode. However, it always treats the external
processor/memory bus as big-endian by performing address
rearrangement and reordering when running in little-endian mode. The
MPC registers in the Raven MPU/PCI bus bridge controller ASIC and the
Falcon memory controller chip set, as well as DRAM, ROM/Flash, and
system registers, always appear as big-endian.
little-endian mode. However, it always treats the external
processor/memory bus as big-endian by performing address
rearrangement and reordering when running in little-endian mode. The
MPC registers in the Raven MPU/PCI bus bridge controller ASIC and the
Falcon memory controller chip set, as well as DRAM, ROM/Flash, and
system registers, always appear as big-endian.
Role of the Raven ASIC
Because the PCI bus is little-endian, the Raven performs byte swapping in
both directions (from PCI to memory and from the processor to PCI) to
maintain address invariance while programmed to operate in big-endian
mode with the processor and the memory subsystem.
both directions (from PCI to memory and from the processor to PCI) to
maintain address invariance while programmed to operate in big-endian
mode with the processor and the memory subsystem.
In little-endian mode, the Raven reverse-rearranges the address for PCI-
bound accesses and rearranges the address for memory-bound accesses
(from PCI). In this case, no byte swapping is done.
bound accesses and rearranges the address for memory-bound accesses
(from PCI). In this case, no byte swapping is done.
PCI Domain
The PCI bus is inherently little-endian. All devices connected directly to
the PCI bus operate in little-endian mode, regardless of the mode of
operation in the processor’s domain.
the PCI bus operate in little-endian mode, regardless of the mode of
operation in the processor’s domain.