Panasonic MN103001G/F01K User Manual
Clock Generator
6-3
6.4
Description of Operation
6.4.1
Input Frequency Setting
The CG input frequency range is set by the external input pin CKSEL. When CKSEL is set “H”, use an oscillator
or resonator with an input frequency fosci such that 8 MHz
or resonator with an input frequency fosci such that 8 MHz
≤
fosci
≤
18 MHz. When CKSEL is set “L”, use an
oscillator or resonator with an input frequency fosci such that 8 MHz
≤
fosci
≤
20 MHz.
Use of an oscillator or resonator that generates a frequency lower than 8 MHz, or higher than 20 MHz is prohibited.
The correspondence between the CKSEL mode and the input frequency range is shown in Table 6-4-1.
Table 6-4-1 CKSEL Mode (PLL used/ PLL not used)
Input frequency range
PLL
CKSEL mode
8 MHz
≤
fosci
≤
18 MHz
When using
H
8 MHz
≤
fosci
≤
20 MHz
When not using
L
6.4.2
Internal Clock Supply
When external input pin CKSEL is “H”, the frequency of the CPU core/internal RAM/bus controller operation
clock (MCLK) is 1x, 2x or 4x the input frequency, depending on the setting of the clock control register, and the
frequency of the internal peripheral function operation clock (IOCLK) is 1/4x MCLK. Note that the clock that is
supplied to external devices (SYSCLK) has the same frequency as the input frequency.
When external input pin CKSEL is “L”, the frequency of the CPU core/internal RAM/bus controller operation
clock (MCLK) is 1/2x the input frequency, and the frequency of the internal peripheral function operation clock
(IOCLK) is 1/8x the input frequency. Note that the clock that is supplied to external devices (SYSCLK) 1/2x the
input frequency.
clock (MCLK) is 1x, 2x or 4x the input frequency, depending on the setting of the clock control register, and the
frequency of the internal peripheral function operation clock (IOCLK) is 1/4x MCLK. Note that the clock that is
supplied to external devices (SYSCLK) has the same frequency as the input frequency.
When external input pin CKSEL is “L”, the frequency of the CPU core/internal RAM/bus controller operation
clock (MCLK) is 1/2x the input frequency, and the frequency of the internal peripheral function operation clock
(IOCLK) is 1/8x the input frequency. Note that the clock that is supplied to external devices (SYSCLK) 1/2x the
input frequency.
Note: For details on the clock control register settings, refer to section 8.6.8, “Clock Control Register.”
When the reset state is released, SYSCLK, MCLK, and IOCLK are supplied starting after a certain oscillation
stabilization wait time.
stabilization wait time.
Note: For details on the oscillation stabilization wait time, refer to Chapter 12, “Watchdog Timer.”
Note 1: When a clock is supplied from external, input the clock to the OSCI pin, and leave the OSCO pin open.
Note 2: The in-circuit emulator (ICE) cannot operate with self-excited oscillators in the microcontroller. Use the
Note 2: The in-circuit emulator (ICE) cannot operate with self-excited oscillators in the microcontroller. Use the
clock generated in the target system.
When the clock is generated in the target system, supply the clock to the in-circuit emulator main unit
through a buffer with adequate drive capability. The in-circuit emulator will not operate correctly if the
amplitude of the clock is inadequate, the clock signal is noisy, or the buffer has inadequate drive capability.
When the clock is generated in the target system, supply the clock to the in-circuit emulator main unit
through a buffer with adequate drive capability. The in-circuit emulator will not operate correctly if the
amplitude of the clock is inadequate, the clock signal is noisy, or the buffer has inadequate drive capability.