Panasonic MN103001G/F01K User Manual
Bus Controller (BC)
8-23
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8.6.6 Refresh count register
Register symbol: REFCNT
Address:
Address:
x'32000042
Purpose:
Sets the DRAM refresh interval when DRAM is connected.
Bit No.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit
REFC REFC REFC REFC REFC REFC REFC REFC REFC REFC REFC REFC REFC REFC REFC REFC
name
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit No.
Bit name
Description
Setting conditions
15 to 0
REFC 15 to 0
DRAM refresh interval
x'0000:
1 SYSCLK
x'FFFF:
65536 SYSCLK
The refresh interval is the (REFCNT setting +1) multiplied by the SYSCLK cycle.
For the DRAM refresh timing, refer to section 8.14.4, “DRAM Refresh.”
For the DRAM refresh timing, refer to section 8.14.4, “DRAM Refresh.”