Panasonic MN103001G/F01K User Manual
Bus Controller (BC)
8-46
Fig. 8-13-17
Access Timing on a 16-bit Bus with Fixed Wait States, in Synchronous Mode and
in Address/Data Multiplex Mode (MCLK = SYSCLK multiplied by 4)
in Address/Data Multiplex Mode (MCLK = SYSCLK multiplied by 4)
For details on the various timing settings, refer to the description of the memory control register in section 8.6,
“Description of Registers.”
8.13.7
16-bit Bus with Fixed Wait States, in Synchronous Mode and in Address/Data Multiplex Mode
By setting the mode through the MMOD1 and 0 pins and the EXMOD1 and 0 pins, blocks 0 to 3 use common pins
for the memory address and memory data signals (pins ADM15 to 0). In synchronous mode, the bus access starts
in synchronization with SYSCLK, and when fixed wait states are inserted, the access ends according to the timing
that was set in the memory control register. The various parameters for external memory access are set in memory
for the memory address and memory data signals (pins ADM15 to 0). In synchronous mode, the bus access starts
in synchronization with SYSCLK, and when fixed wait states are inserted, the access ends according to the timing
that was set in the memory control register. The various parameters for external memory access are set in memory
control registers 0 to 3, corresponding to each block.
BCS indicates the timing during one SYSCLK cycle at which the access should start, and is expressed in terms of
the number of MCLK pulses since the rising edge of SYSCLK.
Fig. 8-13-17 is the timing chart in the case of a “16-bit bus with fixed wait states, in synchronous mode, in address/
data multiplex mode, and with the frequency of MCLK equal to that of SYSCLK multiplied by four.”
Fig. 8-13-18 is the timing chart in the case of a “16-bit bus with fixed wait states, in synchronous mode, in address/
data multiplex mode, and with the frequency of MCLK equal to that of SYSCLK multiplied by two.”
Fig. 8-13-19 is the timing chart in the case of a “16-bit bus with fixed wait states, in synchronous mode, in address/
data multiplex mode, and with the frequency of MCLK equal to that of SYSCLK.”
data multiplex mode, and with the frequency of MCLK equal to that of SYSCLK.”
As shown in each timing chart, the ADM15 to 0 pins go to “Hi-Z” or the undefined output state while CSn is
negated in address/data multiplex mode. When the bus authority is released, the ADM15 to 0 pins are either pulled
up or go to “Hi-Z”, depending on the setting of the I/O port output mode register.
up or go to “Hi-Z”, depending on the setting of the I/O port output mode register.
Note that when writing to byte 0, WE0 is asserted and the data is output on ADM7 to 0, and when writing to byte 1,
WE1 is asserted and the data is output on ADM15 to 8.
WE1 is asserted and the data is output on ADM15 to 8.
Note: For details on the mode settings, refer to Table 8-9-1, “Mode Settings by the BC External Pins.”
Note: “0” (low level) is output on pins A23 to 16 (A23 also serves as CS3) while the ADM15 to 0 pins function as
data pins. Therefore, refer to 3. in section 8.16, “Cautions,” regarding the use of these pins.
AS
CSn
ASA
ADE
RWSEL
MCLK
SYSCLK
BCS
ADM15 to 0
RE
WEn
EA
BCE
BCS
BCE
ASN
ASA
ADE
ASN
EA
REN
WEN
Write
Read
A23* to 16
data in
addr
addr
addr
addr
data out
“0”( )
“L”
: Undefined
: A23 also serves as CS3
*
: Undefined or Hi-Z
“0”( )
“L”