Panasonic MN103001G/F01K User Manual

8-bit Timers

10-3

Fig. 10-3-1 shows a block diagram for timers 0 to 3.
Fig. 10-3-2 shows a block diagram for timers 4 to B.

Figures 10-3-3 to 10-3-6 show connection diagrams for the 8-bit timers.

Fig. 10-3-1

8-bit Timer Block Diagram (Timers 0 to 3)

TMnBR

TMnBC

CK0

CK1

LDE

CNE

TMnMD

TMnIN0
TMnIN1

TMnIN2
TMnIN3

Underflow

Reload

Load

TMnCI

TMnCLK

TMnIRQ

TMnOUT

Cascaded signal from
higher order timer

Underflow interrupt

Timer output

TMnCO

Cascaded signal

Count operation 
enabled

Reset

mode register

base register

binary counter

—

—

—

T

R

Q

Timer n
(n = 0, 1, 2, 3)

CK2

TMnIN5
TMnIN6
TMnIN7

TMnIN4

Clock output