Panasonic MN103001G/F01K User Manual

Watchdog Timer

12-2

This microcontroller has a 25-bit binary counter built in that can be used as a 16- to 25-bit watchdog timer.
A watchdog timer overflow generates a nonmaskable interrupt, enabling the watchdog timer overflow to be identified.
The watchdog timer is also used as an oscillation stabilization wait timer.

• The number of bits in the binary counter is selectable.

When the CKSEL pin input is "H" (oscillating frequency: 8 MHz to 18 MHz):

16, 18, 20, 22, or 24 bits can be selected.

When the CKSEL pin input is "L" (oscillating frequency: 8 MHz to 20 MHz):

17, 19, 21, 23, or 25 bits can be selected.

Overflow cycle: 4.369 ms to 1118.481 ms

(when the CKSEL pin input is "H" and the oscillating frequency is 15 MHz)

• A non-maskable interrupt is generated when a watchdog timer overflow occurs.
• Watchdog timer overflow output

A flag can be set to "1" when a watchdog timer overflow occurs.
The watchdog timer overflow output can be selected as either pulse output or level output.

• Oscillation stabilization wait time (when the CKSEL pin input is "H" and the oscillating frequency is

15 MHz)

When reset is released:

17.476 ms

When recovering from STOP mode: 4.369 ms to 1118.481 ms <Recommended value is 14 ms or longer.>

• The chip can self-reset internally by writing the RSTCTR register.