Panasonic MN103001G/F01K User Manual

Watchdog Timer

12-7

Oscillation stabilization wait operation

The watchdog timer operates as an oscillation stabilization wait timer after the reset state is released or when the
microcontroller recovers from STOP mode (Fig. 12-5-1).
The watchdog timer operates in this capacity even if the WDCNE flag is "0".

When recovering from STOP mode, the watchdog timer operates as a counter of the number of bits specified by

WDCK2 to 0 (Fig. 12-5-2).  The oscillation stabilization wait time can be selected from among times that are

calculated as follows:

Overflow cycle = 2

(n + WDCK x 2)

/(f x 10

3

) [ms]

Where, n = 16 (CKSEL pin is “H”) or n = 17 (CKSEL pin is “L”);  WDCK = WDCK[2:0]; f: Oscillation

input frequency [unit: MHz]

An oscillation stabilization wait time of at least 14 ms is recommended.

If the WDCNE flag is "1", a non-maskable interrupt is not generated even when recovering from STOP mode.

Fig. 12-5-1   Operation Diagram 1: When Reset Is Released

Watchdog timer 
count value

Overflow

(when CKSEL = “H” and the oscillating input frequency is 15 MHz)

Internal clock, 

SYSCLK supply 

enabled

SYSCLK 8 cycle width

17.476 ms

Oscillation stabilization 
wait time

SYSCLK

Internal reset

RST pin

OSCI input