Epson S1F70000 User Manual

S1F70000 Series

3–35

Technical Manual

The markings on S1F79100Y series device packages
use the following abbreviations.

Voltage regulator
code

Output voltage
code

The S1F79100Y series uses a 3-pin series regulator
feedback loop.  An operational amplifier compares
V

REG

 from the voltage divider formed by R

1

 and R

2

,

with V

REF

.  The amplifier output adjusts the output

transistor gate bias to equalize the voltages and com-
pensate for fluctuations in V

I

.

V

REF

GND

V

O

R

1

V

REG

R

2

V

I

–

+

The following equation shows the relationship between
V

O

 and V

REF

.

R

1

 + R

2

V

O

  = ————— V

REF

R

1

Output voltage code

B

5  V

D

3  V

Voltage regulator code

P

Positive

N

Negative

Note
The reflow furnace temperature profile requirements
must be satisfied during package reflow.  Avoid solder-
ing on surface mount package (including SOT89) as it
causes a quick temperature change of package and a
device damage.

The offset structure used in all three transistors results
in a high breakdown voltage that ensures a stable refer-
ence voltage output over a wide range of input voltages.

V

REF

V

1

V

SS

Enhancement
      mode

Depletion
   mode

Depletion
   mode