Fluke 2625A User Manual
Diagnostic Testing and Troubleshooting (2620A/2625A)
Digital and Alarm Output Troubleshooting
5
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5-15. Digital and Alarm Output Troubleshooting
Power up Hydra while holding down the CANCL button to reset the instrument
configuration. Since the structure of the eight Digital Outputs and four Alarm Outputs is
very similar, the troubleshooting procedure presented here does not refer to specific
device and pin numbers. First verify that the input of the Output Driver (A1U17 or
A1U27) is low and that the output is near +5V dc. If the input is high, the problem may
be in the address decoding (A1U12 and A1U15) or the associated octal D-type flip-flop
(A1U16 or A1U26). If the output is not near +5V dc, use an ohmmeter to check the pull-
up resistor in A1Z2.
configuration. Since the structure of the eight Digital Outputs and four Alarm Outputs is
very similar, the troubleshooting procedure presented here does not refer to specific
device and pin numbers. First verify that the input of the Output Driver (A1U17 or
A1U27) is low and that the output is near +5V dc. If the input is high, the problem may
be in the address decoding (A1U12 and A1U15) or the associated octal D-type flip-flop
(A1U16 or A1U26). If the output is not near +5V dc, use an ohmmeter to check the pull-
up resistor in A1Z2.
Use the proper computer interface command to change the state of the Digital Output
(DO_LEVEL x,1) or Alarm Output (ALARM_DO_LEVEL x,1), where x is the number
of the output being checked. Now verify that the input of the Output Driver is high and
that the output is near +0.8V dc. If there is no change in the input, check the address
decoding and operation of the associated octal D-type flip-flop (A1U16 or A1U26.) If
the output failed to change, the problem is most likely the inverting output driver
(A1U17 or A1U27).
(DO_LEVEL x,1) or Alarm Output (ALARM_DO_LEVEL x,1), where x is the number
of the output being checked. Now verify that the input of the Output Driver is high and
that the output is near +0.8V dc. If there is no change in the input, check the address
decoding and operation of the associated octal D-type flip-flop (A1U16 or A1U26.) If
the output failed to change, the problem is most likely the inverting output driver
(A1U17 or A1U27).
5-16. Digital Input Troubleshooting
Power up Hydra while holding down the CANCL button to reset the instrument
configuration. Verify that the Input Buffer Threshold circuit generates approximately
1.4V dc at A1TP18. Drive the Digital Input (A1J5) to be checked with a signal generator
outputting a 100-Hz square wave that transitions from 0 to +5V dc. The signal generator
output common should be connected to Common (A1J5-1). Verify that the output of the
Input Buffer is a 100 Hz square wave that is the inverse of the input signal.
configuration. Verify that the Input Buffer Threshold circuit generates approximately
1.4V dc at A1TP18. Drive the Digital Input (A1J5) to be checked with a signal generator
outputting a 100-Hz square wave that transitions from 0 to +5V dc. The signal generator
output common should be connected to Common (A1J5-1). Verify that the output of the
Input Buffer is a 100 Hz square wave that is the inverse of the input signal.
If the Input Buffer does not function correctly, the problem is probably A1Z1, A1Z3, or
the associated comparator (A1AR2 or A1AR3). If the Input Buffer functions correctly,
but Hydra is not able to read the state of the Digital Input correctly, the problem is most
likely the tri-state buffer A1U13. If Hydra is not able to read the states of any of the
eight Digital Inputs correctly, the problem is most likely the address decoding (A1U10
and A1U12) for the tri-state buffer.
the associated comparator (A1AR2 or A1AR3). If the Input Buffer functions correctly,
but Hydra is not able to read the state of the Digital Input correctly, the problem is most
likely the tri-state buffer A1U13. If Hydra is not able to read the states of any of the
eight Digital Inputs correctly, the problem is most likely the address decoding (A1U10
and A1U12) for the tri-state buffer.
5-17. Totalizer Troubleshooting
Power up Hydra while holding down the CANCL button to reset the instrument
configuration. Verify that the Input Buffer Threshold circuit generates approximately
1.4V dc at A1TP18. Drive the Totalizer Input (A1J5-2) with a signal generator
outputting a 100-Hz square wave that transitions from 0 to +5V dc. The signal generator
output common should be connected to Common (A1J5-1). Verify that the output of the
Input Buffer (A1AR1-7) is a 100-Hz square wave that is the inverse of the input signal.
Verify also that the input to the totalizer counter (A1TP20) is a buffered form of the
signal just verified at the output of the Input Buffer.
configuration. Verify that the Input Buffer Threshold circuit generates approximately
1.4V dc at A1TP18. Drive the Totalizer Input (A1J5-2) with a signal generator
outputting a 100-Hz square wave that transitions from 0 to +5V dc. The signal generator
output common should be connected to Common (A1J5-1). Verify that the output of the
Input Buffer (A1AR1-7) is a 100-Hz square wave that is the inverse of the input signal.
Verify also that the input to the totalizer counter (A1TP20) is a buffered form of the
signal just verified at the output of the Input Buffer.
Use the following procedure to troubleshoot the totalizer input debouncer, Enable the
totalizer debouncer by sending the TOTAL_DBNC 1 Computer Interface command to
the instrument; verify that A1U16-16 is now high. With the signal generator still
connected and outputting a 100-Hz square wave, verify that A1U14 drives the clear input
of the counter (A1U20-11) low for 1.67 milliseconds after each edge of the input signal.
Verify that counter output A1U20-13 generates a 4.8-kHz clock while A1U20-11 is low.
Verify that the shift register output (A1U29-9) changes to the same state as the totalizer
input signal about 1.67 milliseconds after a transition occurs on the totalizer input signal
(A1U29-10).
totalizer debouncer by sending the TOTAL_DBNC 1 Computer Interface command to
the instrument; verify that A1U16-16 is now high. With the signal generator still
connected and outputting a 100-Hz square wave, verify that A1U14 drives the clear input
of the counter (A1U20-11) low for 1.67 milliseconds after each edge of the input signal.
Verify that counter output A1U20-13 generates a 4.8-kHz clock while A1U20-11 is low.
Verify that the shift register output (A1U29-9) changes to the same state as the totalizer
input signal about 1.67 milliseconds after a transition occurs on the totalizer input signal
(A1U29-10).