Fluke 2625A User Manual
HYDRA
Service Manual
2-16
2-47. Totalizer
Input
The Totalizer Input circuit consists of Input Protection, a Digital Input Buffer circuit,
and a Totalizer Debouncer circuit. The Digital Input Buffer for the totalizer is protected
from electrostatic discharge (ESD) damage by A1R49 and A1C43. Refer to the detailed
description of the Digital Input Buffer circuit for more information.
and a Totalizer Debouncer circuit. The Digital Input Buffer for the totalizer is protected
from electrostatic discharge (ESD) damage by A1R49 and A1C43. Refer to the detailed
description of the Digital Input Buffer circuit for more information.
The Totalizer Debounce circuit allows the Microprocessor to select totalizing of either
the input signal or the debounced input signal. Latch output A1U16-16 is set low by
A1U4 to totalize the unmodified input signal or high to totalize the debounced input
signal. This totalizer clock control is provided by A1U28; output A1U28-3 drives the
totalizer counter clock input (A1U2-4).
the input signal or the debounced input signal. Latch output A1U16-16 is set low by
A1U4 to totalize the unmodified input signal or high to totalize the debounced input
signal. This totalizer clock control is provided by A1U28; output A1U28-3 drives the
totalizer counter clock input (A1U2-4).
The actual debouncing of the input signal is accomplished by A1U14, A1U20, and
A1U29. An EXOR gate compares the input signal (A1U14-13) and the output of an
eight-bit shift register (A1U29-9). If these signals differ, EXOR gate output A1U14-11
goes high, enabling counter A1U20 and shift register A1U29. The counter divides the
system clock of 1.2288 MHz (A1U20-10) by 256 to yield a 4.8-kHz clock (A1U20-13).
This signal clocks the eight-bit shift register. After approximately 1.5625 milliseconds,
the input signal will have been shifted from the serial input (A1U29-10) through to the
eighth output bit (A1U29-9). This forces the counter and shift register to stop. If the
input signal changes state before 1.5625 milliseconds have elapsed, the counter is
cleared and the shift register is preloaded again. Therefore, the input signal must remain
stable for greater than 1.5625 milliseconds before that transition changes the state of the
clock input of the totalizer counter (A1U2-4).
A1U29. An EXOR gate compares the input signal (A1U14-13) and the output of an
eight-bit shift register (A1U29-9). If these signals differ, EXOR gate output A1U14-11
goes high, enabling counter A1U20 and shift register A1U29. The counter divides the
system clock of 1.2288 MHz (A1U20-10) by 256 to yield a 4.8-kHz clock (A1U20-13).
This signal clocks the eight-bit shift register. After approximately 1.5625 milliseconds,
the input signal will have been shifted from the serial input (A1U29-10) through to the
eighth output bit (A1U29-9). This forces the counter and shift register to stop. If the
input signal changes state before 1.5625 milliseconds have elapsed, the counter is
cleared and the shift register is preloaded again. Therefore, the input signal must remain
stable for greater than 1.5625 milliseconds before that transition changes the state of the
clock input of the totalizer counter (A1U2-4).
2-48. External Trigger Input Circuits
The External Trigger Input circuit can be configured by the Microprocessor to interrupt
on a rising or falling edge of the XT* input (A1J6-2) or to not interrupt on any
transitions of the XT* input.
on a rising or falling edge of the XT* input (A1J6-2) or to not interrupt on any
transitions of the XT* input.
The Microprocessor sets latch output A1U16-19 high for falling edge detection and low
for rising edge detection of the XT* input. The Microprocessor can enable the external
trigger interrupt by setting port pin A1U4-28 high or disable the interrupt by setting it
low. Microprocessor port pin A1U4-28 should only be high if the instrument trigger
mode of "ON" has been selected. Resistor A1R20 pulls NAND gate input A1U13 low
during power-up to ensure that the external trigger interrupt input (A1U4-9) is high.
for rising edge detection of the XT* input. The Microprocessor can enable the external
trigger interrupt by setting port pin A1U4-28 high or disable the interrupt by setting it
low. Microprocessor port pin A1U4-28 should only be high if the instrument trigger
mode of "ON" has been selected. Resistor A1R20 pulls NAND gate input A1U13 low
during power-up to ensure that the external trigger interrupt input (A1U4-9) is high.
When the EXOR gate output (A1U14-3) goes high, and NAND gate input A1U12-13 is
high, the output of the NAND gate (A1U12-11) goes low to interrupt the
Microprocessor. The Microprocessor can also determine the state of the XT* input by
reading the TRIG signal on port pin A1U4-27.
high, the output of the NAND gate (A1U12-11) goes low to interrupt the
Microprocessor. The Microprocessor can also determine the state of the XT* input by
reading the TRIG signal on port pin A1U4-27.
The XT* input is pulled up to +5V dc by A1Z2 and is protected from damage by ESD by
A1R58, A1C54, A1Z3, and A1CR15. Capacitor A1C54 helps ensure that the instrument
meets EMI/EMC performance requirements.
A1R58, A1C54, A1Z3, and A1CR15. Capacitor A1C54 helps ensure that the instrument
meets EMI/EMC performance requirements.
2-49. A/D Converter PCA
The following paragraphs describe the operation of the circuits on the A/D Converter
PCA. The schematic for this pca is located in Section 8.
PCA. The schematic for this pca is located in Section 8.
2-50. Analog Measurement Processor
Refer to Figure 2-3 for an overall picture of the Analog Measurement Processor chip and
its peripheral circuits. Table 2-4 describes Analog Measurement Processor chip signal
names.
its peripheral circuits. Table 2-4 describes Analog Measurement Processor chip signal
names.