Fluke 2625A User Manual
HYDRA
Service Manual
2A-10
2A-29. Inverter Inguard Supply
The inverter inguard supply provides three outputs: +5.3V dc (VDD) and -5.4V dc
(VSS) for the inguard analog and digital circuitry, and +5.6V dc (VDDR) for the relays.
Diodes A1CR5 and A1CR6, and capacitor A1C12 are for the +9.5 volt source, and
diodes A1CR7 and capacitor A1C13 are for the -9.5V source.
(VSS) for the inguard analog and digital circuitry, and +5.6V dc (VDDR) for the relays.
Diodes A1CR5 and A1CR6, and capacitor A1C12 are for the +9.5 volt source, and
diodes A1CR7 and capacitor A1C13 are for the -9.5V source.
Three-terminal regulator A1U6 regulates the 9.5V source to 5.6V for the relays. A1R5
and A1R6 set the output voltage at 5.6V. A1C6 is required for transient performance.
The +5.3V regulator circuit uses A1Q2 for the series-pass element and A1Q4 as the error
amplifier. A1VR2 is the reference for the positive supply. A1R14 provides the current to
bias the reference zener. A1C4 is the output filter, and A1C9 provides frequency
compensation of the regulator circuit. Transistor A1Q1 and resistor A1R13 make up the
current-limit circuit.
and A1R6 set the output voltage at 5.6V. A1C6 is required for transient performance.
The +5.3V regulator circuit uses A1Q2 for the series-pass element and A1Q4 as the error
amplifier. A1VR2 is the reference for the positive supply. A1R14 provides the current to
bias the reference zener. A1C4 is the output filter, and A1C9 provides frequency
compensation of the regulator circuit. Transistor A1Q1 and resistor A1R13 make up the
current-limit circuit.
When the voltage across A1R13 increases enough to turn on A1Q1, output current is
limited by removing the base drive to A1Q2.
limited by removing the base drive to A1Q2.
The -5.4 volt regulator operates like the +5.3 volt regulator, except that the NPN
transistors in the positive supply are PNP transistors in the negative supply, and the PNP
transistors in the positive supply are NPN transistors in the negative supply. If a VDD-
to-VSS short circuit occurs, diode A1CR4 ensures that current limit occurs at the limit
set for the -5.4V dc or +5.3V dc supply, whichever is lower.
transistors in the positive supply are PNP transistors in the negative supply, and the PNP
transistors in the positive supply are NPN transistors in the negative supply. If a VDD-
to-VSS short circuit occurs, diode A1CR4 ensures that current limit occurs at the limit
set for the -5.4V dc or +5.3V dc supply, whichever is lower.
2A-30. Power Fail Detection
The power fail detection circuit generates a signal to warn the Microprocessor that the
power supply is going down. A comparator in A1U10 compares the divided-down raw
supply voltage to a voltage reference internal to A1U10. When the raw supply voltage is
greater than about 8V dc, the output of A1U10 is "high" and when the raw supply falls
below 8V dc, the output goes "low". Resistors A1R19 and A1R20 make up the divider,
and capacitor A1C74 provides filtering of high frequency noise at the comparator input.
The reference voltage internal to A1U10 is nominally 1.3 volts dc.
power supply is going down. A comparator in A1U10 compares the divided-down raw
supply voltage to a voltage reference internal to A1U10. When the raw supply voltage is
greater than about 8V dc, the output of A1U10 is "high" and when the raw supply falls
below 8V dc, the output goes "low". Resistors A1R19 and A1R20 make up the divider,
and capacitor A1C74 provides filtering of high frequency noise at the comparator input.
The reference voltage internal to A1U10 is nominally 1.3 volts dc.
2A-31. Digital Kernel
The Digital Kernel is composed of the following nine functional circuit blocks: the Reset
Circuits, the Microprocessor, the Address Decoding, the Flash Memory, the Nonvolatile
Static RAM and Real-Time Clock, the FPGA (Field Programmable Gate Array), the
Serial Communication (Guard Crossing), the RS-232 Interface, and the Option Interface.
Circuits, the Microprocessor, the Address Decoding, the Flash Memory, the Nonvolatile
Static RAM and Real-Time Clock, the FPGA (Field Programmable Gate Array), the
Serial Communication (Guard Crossing), the RS-232 Interface, and the Option Interface.
2A-32. Reset Circuits
The Power-On Reset signal (POR*, A1U10-7) is generated by the Microprocessor
Supervisor, which monitors the voltage of VCC at A1U10-2. If VCC is less than +4.65
volts, then A1U10-7 will be driven low. POR* drives the enable inputs of the four tri-
state buffers in A1U2, causing the HALT*, RESET*, ORST*, and DRST* signals to be
driven low when POR* is low. When POR* goes high, the tri-state buffer outputs
(A1U2) go to their high-impedance state and the pull-up resistors pull the outputs to a
high level.
Supervisor, which monitors the voltage of VCC at A1U10-2. If VCC is less than +4.65
volts, then A1U10-7 will be driven low. POR* drives the enable inputs of the four tri-
state buffers in A1U2, causing the HALT*, RESET*, ORST*, and DRST* signals to be
driven low when POR* is low. When POR* goes high, the tri-state buffer outputs
(A1U2) go to their high-impedance state and the pull-up resistors pull the outputs to a
high level.
When HALT* and RESET* are both driven low, the Microprocessor (A1U1) is reset and
will begin execution when they both go high. The Microprocessor may execute a "reset"
instruction during normal operation to drive A1U1-92 low for approximately 10
microseconds to reset all system hardware connected to the RESET* signal.
will begin execution when they both go high. The Microprocessor may execute a "reset"
instruction during normal operation to drive A1U1-92 low for approximately 10
microseconds to reset all system hardware connected to the RESET* signal.