SMSC LAN9311 User Manual
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9311/LAN9311i
153
Revision 1.4 (08-19-08)
DATASHEET
The
defaults as detailed in
The
is written with the new defaults
as detailed in
The
is written with the new defaults
as detailed in
. Additionally, the Restart Auto-negotiation bit is set in this register. This re-runs the Auto-
negotiation using the new default values of the
register to determine the new Auto-negotiation results.
Note:
Each of these PHY registers is written in its entirety, overwriting any previously changed bits.
10.2.4.4.2
VIRTUAL PHY REGISTERS SYNCHRONIZATION
Some PHY register defaults are based on configuration straps. In order to maintain consistency
between the updated configuration strap registers and the Virtual PHY registers, the
between the updated configuration strap registers and the Virtual PHY registers, the
, a n d
are written when the EEPROM Loader is run.
The
is written with the new
defaults as detailed in
.
The
is written
with the new defaults as detailed in
.
The
detailed in
.
Additionally, the Restart Auto-negotiation bit is set in this register. This re-runs the Auto-negotiation
using the new default values of the
using the new default values of the
register to determine the new Auto-negotiation results.
Note:
Each of these VPHY registers is written in its entirety, overwriting any previously changed bits.
10.2.4.4.3
LED AND MANUAL FLOW CONTROL REGISTER SYNCHRONIZATION
,
, and
are based on configuration straps, the EEPROM
Loader reloads these registers with their new default values.
10.2.4.5
Register Data
Optionally following the configuration strap values, the EEPROM data may be formatted to allow
access to the LAN9311/LAN9311i parallel, directly writable registers. Access to indirectly accessible
registers (e.g. Switch Engine registers, etc.) is achievable with an appropriate sequence of writes (at
the cost of EEPROM space).
access to the LAN9311/LAN9311i parallel, directly writable registers. Access to indirectly accessible
registers (e.g. Switch Engine registers, etc.) is achievable with an appropriate sequence of writes (at
the cost of EEPROM space).
This data is first preceded with a Burst Sequence Valid Flag (EEPROM byte 12). If this byte has a
value of A5h, the data that follows is recognized as a sequence of bursts. Otherwise, the EEPROM
Loader is finished, will go into a wait state, and clear the EPC_BUSY bit in the
value of A5h, the data that follows is recognized as a sequence of bursts. Otherwise, the EEPROM
Loader is finished, will go into a wait state, and clear the EPC_BUSY bit in the
. This can optionally generate an interrupt.
The data at EEPROM byte 13 and above should be formatted in a sequence of bursts. The first byte
is the total number of bursts. Following this is a series of bursts, each consisting of a starting address,
count, and the count x 4 bytes of data. This results in the following formula for formatting register data:
is the total number of bursts. Following this is a series of bursts, each consisting of a starting address,
count, and the count x 4 bytes of data. This results in the following formula for formatting register data: