SMSC LAN9311 User Manual

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

Revision 1.4 (08-19-08)

158

SMSC LAN9311/LAN9311i

 

Clock synchronization and hardware processing between the network data and the time stamp capture
hardware causes the time stamp point to be slightly delayed. The host software can account for this
delay, as it is fairly deterministic. 

 details the time stamp capture delay as a function of the

mode of operation. Refer to 

 for details on these modes.

Once the packet type is matched, according to 

, and the Frame Check Sequence (FCS) is

verified, the following occurs:

„

The time stamp is loaded into the corresponding ports’ capture registers:

–On Reception: 

 and 

–On Transmission: 

„

The Sequence ID and Source UUID are loaded into the corresponding ports’ registers:

–On Reception: 

 and 

–On Transmission: 

 and 

„

The corresponding maskable interrupt flag is set in the 

. (Refer to 

 for information 

on IEEE 1588 interrupts.)

Packets that do not contain an integral number of octets are not considered valid and do not
cause a capture.

The corresponding ports’ clock capture, sequence ID, and source UUID registers can be optionally
locked when a capture event occurs, preventing them from being overwritten until the host clears the
corresponding interrupt flag in the 

.

This is accomplished by setting the corresponding lock enable bit(s) in the 

. Each port has two lock enable control bits within this register, which allow the receive

and transmit portions of each port to be locked independently. In addition, a lock enable bit is provided
for each time stamp enabled GPIO (LOCK_ENABLE_GPIO_8 and LOCK_ENABLE_GPIO_9) which
prevents the corresponding GPIO clock capture registers from being overwritten when the GPIO
interrupt in 

 is set. Refer to 

 for additional information on

the capture locking related bits.

100 Mbps

30 nS

10 Mbps

120 nS