SMSC LAN9311 User Manual

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

SMSC LAN9311/LAN9311i

193

Revision 1.4 (08-19-08)

 

This section details the General Purpose I/O (GPIO) and LED related System CSR’s.

This read/write register configures the GPIO input and output pins. The polarity of the 12 GPIO pins
is configured here as well as the IEEE 1588 timestamping and clock compare event output properties
of the GPIO[9:8] pins.

Offset:

1E0h

Size:

32 bits

31:30

RO

-

29:28

GPIO 1588 Timer Interrupt Clear Enable 9-8 
(GPIO_1588_TIMER_INT_CLEAR_EN[9:8])
These bits enable inputs on GPIO9 and GPIO8 to clear the 
1588_TIMER_INT bit of the 

. The polarity of these inputs is determined by 

GPIO_INT_POL[9:8].

The GPIO must be configured as an input for this function to 
operate. For the clear function, GPIO inputs are edge sensitive and 
must be active for greater than 40 nS to be recognized.

R/W

00b

27:16

GPIO Interrupt Polarity 11-0 (GPIO_INT_POL[11:0])
These bits set the interrupt polarity of the 12 GPIO pins. The configured 
level (high/low) will set the corresponding GPIO_INT bit in the 

.

GPIO_INT_POL[9:8] also determines the polarity of the GPIO IEEE 1588 
time clock capture events and the GPIO 1588 Timer Interrupt Clear inputs. 
Refer to 

 for additional 

information.

R/W

0h

15:14

1588 GPIO Output Enable 9-8 (1588_GPIO_OE[9:8])
These bits configure GPIO 9 and GPIO 8 to output 1588 clock compare 
events. 

These bits override the direction bits in the 

 register. However, 

the GPIO buffer type (GPIOBUF[11:0]) in the 

 is not overridden.

R/W

0h

13

GPIO 9 Clock Event Polarity (GPIO_EVENT_POL_9)
This bit determines if the 1588 clock event output on GPIO 9 is active high 
or low.

R/W

1b

12

GPIO 8 Clock Event Polarity (GPIO_EVENT_POL_8)
This bit determines if the 1588 clock event output on GPIO 8 is active high 
or low.

R/W

1b